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CD32 Expansion-port

182 PIN (SAME AS MCA) (At the computer)

UNKNOWN 182 PIN CONNECTOR (SAME AS MCA) at the computer.

PinNameDescriptionComment
1 A31 Address 31 Probably not connected since 68EC020
2 A30 Address 30 Probably not connected since 68EC020
3 A29 Address 29 Probably not connected since 68EC020
4 A28 Address 28 Probably not connected since 68EC020
5 A27 Address 27 Probably not connected since 68EC020
6 A26 Address 26 Probably not connected since 68EC020
7 A25 Address 25 Probably not connected since 68EC020
8 A24 Address 24
9 DGND Data Ground
10 VCC +5 VDC
11 A23 Address 23
12 A22 Address 22
13 A21 Address 21
14 A20 Address 20
15 A19 Address 19
16 A18 Address 18
17 A17 Address 17
18 A16 Address 16
19 DGND Data Ground
20 VCC +5 VDC
21 A15 Address 15
22 A14 Address 14
23 A13 Address 13
24 A12 Address 12
25 A11 Address 11
26 A10 Address 10
27 A9 Address 9
28 A8 Address 8
29 DGND Data Ground
30 VCC +5 VDC
31 A7 Address 7
32 A6 Address 6
33 A5 Address 5
34 A4 Address 4
35 A3 Address 3
36 A2 Address 2
37 A1 Address 1
38 A0 Address 0
39 DGND Data Ground
40 VCC +5 VDC
41 D31 Data 31
42 D30 Data 30
43 D29 Data 29
44 D28 Data 28
45 D27 Data 27
46 D26 Data 26
47 D25 Data 25
48 D24 Data 24
49 DGND Data Ground
50 VCC +5 VDC
51 D23 Data 23
52 D22 Data 22
53 D21 Data 21
54 D20 Data 20
55 D19 Data 19
56 D18 Data 18
57 D17 Data 17
58 D16 Data 16
59 DGND Data Ground
60 VCC +5 VDC
61 D15 Data 15
62 D14 Data 14
63 D13 Data 13
64 D12 Data 12
65 D11 Data 11
66 D10 Data 10
67 D9 Data 9
68 D8 Data 8
69 DGND Data Ground
70 VCC +5 VDC
71 D7 Data 7
72 D6 Data 6
73 D5 Data 5
74 D4 Data 4
75 D3 Data 3
76 D2 Data 2
77 D1 Data 1
78 D0 Data 0
79 DGND Data Ground
80 VCC +5 VDC
81 /IPL2 Interrupt Priority Level 2
82 /IPL1 Interrupt Priority Level 1
83 /IPL0 Interrupt Priority Level 0
84
85 /RST Reset
86 /HALT Halt
87 /ECS ECS??
88 /OCS OCS??
89 SIZE1 Size 1 Indicates number of bytes remaining to transfer
90 SIZE0 Size 0 Indicates number of bytes remaining to transfer
91 /AS Address Strobe
92 /DS Data Strobe
93 /R/W Read/Write
94 /BERR Bus Error
95
96 /AVEC Autovector Req Autovector request during interrupt acknowledge
97 /DSACK1 Data Ack 1 Data trasnfer and size acknowledge
98 /DSACK0 Data Ack 0 Data transfer and size acknowledge
99 CPUCLK_A
100
101 DGND Data Ground
102 VCC +5 VDC
103 FC2 Function Codes 2
104 FC1 Function Codes 1
105 FC0 Function Codes 0
106
107
108
109
110
111 /CPU_BR CPU bus request??
112 /EXP_BG Expansion bus granted??
113 /CPU_BG CPU bus granted??
114 /EXP_BR Expansion bus request??
115
116
117 /PUNT
118 /RESET 68020 RESET
119 /INT2 Interrupt 2 Generate a level 2 interrupt
120 /INT6 Interrupt 2 Generate a level 6 interrupt
121 /KB_CLOCK Keyboard clock
122 /KB_DATA Keyboard data
123 /FIRE0 Fire Button 0??
124 /FIRE1 Fire Button 1??
125 /LED Power On LED ??
126 /ACTIVE Disk active LED
127 /RXD Serial Receive Serial data in
128 /TXD Serial Transmit Serial data out
129 /DKRD Floppy interface (Paula?)
130 /DKWD Floppy interface (Paula?)
131 SYSTEM
132 /DKWE Floppy interface (Paula?)
133 CONFIG_OUT
134
135 DGND Data Ground
136 +12V +12V DC
137 DGND Data Ground
138 +12V +12V DC
139 17MHZ For FMV inteface ??
140 EXT_AUDIO For FMV inteface ??
141 DA_DATA For FMV inteface ??
142 /MUTE For FMV inteface ??
143 DA_LRCLK For FMV inteface ??
144 DA_BCLK For FMV inteface ??
145 DGND Data Ground
146 VCC +5 VDC
147 DR Digital Red
148 DG Digital Green
149 DB Digital Blue
150 DI Digital Intensity
151 /PIXELSW_EXT
152 /PIXELSW
153 /BLANK
154 PIXELCLK Pixelclock For manipulating RBG data
155 DGND Data Ground
156 VCC +5 VDC
157 /CSYNC Composite sync Not buffered.
158 CCK_B Color clock ??
159 /HSYNC Horizontal sync
160 /VSYNC Vertical sync
161 VGND Video ground
162 VGND Video ground
163 AR_EXT Analog Red External
164 AR Analog Red
165 AG_EXT Analog Green External
166 AG Analog Green
167 AB_EXT Analog Blue External
168 AB Analog Blue
169 VGND Video ground
170 VGND Video ground
171 /NTSC
172 /XCLKEN Enable External video clock (Genlock)
173 XCLK External video clock (Genlock)
174 /EXT_VIDEO External Video Disable internal video interfaces
175 DGND Data Ground
176 VCC +5 VDC
177 AGND Audio Ground
178 +12V +12V DC
179 LEFT_EXT Left sound External
180 LEFT Left sound
181 RIGHT_EXT Right sound External
182 RIGHT Right sound
 
 

EISA

EISA=Extended Industry Standard Architecture.
Developed by Compaq, AST, Zenith, Tandy...

+---------------------------------------------+
|            (component side)                 |
|                                             |
|___________ ISA-16bit __       ISA-8bit    __|
            |||||||||||  |||||||||||||||||||  A1(front)/B1(back)
             | | | | |    | | | | | | | | |  EISA: E1(front)/F1(back)
                   C1/D1
                  G1/H1
A,C,E,G=Component Side
A,B,F,H=Sold Side

NOT DRAWN YET (At the computer)

62+38 PIN EDGE CONNECTOR at the computer.

Pin Name Description
E1 CMD# Command Phase
E2 START# Start Phase
E3 EXRDY EISA Ready
E4 EX32# EISA Slave Size 32
E5 GND Ground
E6 KEY Access Key
E7 EX16# EISA Slave Size 16
E8 SLBURST# Slave Burst
E9 MSBURST# Master Burst
E10 W/R# Write/Read
E11 GND Ground
E12 RES Reserved
E13 RES Reserved
E14 RES Reserved
E15 GND Ground
E16 KEY Access Key
E17 BE1# Byte Enable 1
E18 LA31# Latchable Addressline 31
E19 GND Ground
E20 LA30# Latchable Addressline 30
E21 LA28# Latchable Addressline 28
E22 LA27# Latchable Addressline 27
E23 LA25# Latchable Addressline 25
E24 GND Ground
E25 KEY Access Key
E26 LA15 Latchable Addressline 15
E27 LA13 Latchable Addressline 13
E28 LA12 Latchable Addressline 12
E29 LA11 Latchable Addressline 11
E30 GND Ground
E31 LA9 Latchable Addressline 9
     
F1 GND Ground
F2 +5V +5 VDC
F3 +5V +5 VDC
F4 ---  
F5 ---  
F6 KEY Access Key
F7 ---  
F8 ---  
F9 +12V +12 VDC
F10 M/IO# Memory/Input-Output
F11 LOCK# Lock bus
F12 RES Reserved
F13 GND Ground
F14 RES Reserved
F15 BE3# Byte Enable 3
F16 KEY Access Key
F17 BE2# Byte Enable 2
F18 BE0# Byte Enable 0
F19 GND Ground
F20 +5V +5 VDC
F21 LA29# Latchable Addressline 29
F22 GND Ground
F23 LA26# Latchable Addressline 26
F24 LA24# Latchable Addressline 24
F25 KEY Access Key
F26 LA16 Latchable Addressline 16
F27 LA14 Latchable Addressline 14
F28 +5V +5 VDC
F29 +5V +5 VDC
F30 GND Ground
F31 LA10 Latchable Addressline 10
     
G1 LA7 Latchable Addressline 7
G2 GND Ground
G3 LA4 Latchable Addressline 4
G4 LA3 Latchable Addressline 3
G5 GND Ground
G6 KEY Access Key
G7 D17 Data 17
G8 D19 Data 19
G9 D20 Data 20
G10 D22 Data 22
G11 GND Ground
G12 D25 Data 25
G13 D26 Data 26
G14 D28 Data 28
G15 KEY Access Key
G16 GND Ground
G17 D30 Data 30
G18 D31 Data 31
G19 MREQx Master Request
     
H1 LA8 Latchable Addressline 8
H2 LA6 Latchable Addressline 6
H3 LA5 Latchable Addressline 5
H4 +5V +5 VDC
H5 LA2 Latchable Addressline 2
H6 KEY Access Key
H7 D16 Data 16
H8 D18 Data 18
H9 GND Ground
H10 D21 Data 21
H11 D23 Data 23
H12 D24 Data 24
H13 GND Ground
H14 D27 Data 27
H15 KEY Access Key
H16 D29 Data 29
H17 +5V +5 VDC
H18 +5V +5 VDC
H19 MAKx Master Acknowledge
 
 
0

ISA

  • 23-02-2009, 23:52
  • Просмотров: 2734
 

ISA

ISA=Industry Standard Architecture

62+36 PIN EDGE CONNECTOR MALE (At the card)
62+36 PIN EDGE CONNECTOR FEMALE (At the computer)

62+36 PIN EDGE CONNECTOR MALE at the card.
62+36 PIN EDGE CONNECTOR FEMALE at the computer.

Pin Name Dir Description
A1 /I/O CH CK <-- I/O channel check; active low=parity error
A2 D7 <-> Data bit 7
A3 D6 <-> Data bit 6
A4 D5 <-> Data bit 5
A5 D4 <-> Data bit 4
A6 D3 <-> Data bit 3
A7 D2 <-> Data bit 2
A8 D1 <-> Data bit 1
A9 D0 <-> Data bit 0
A10 I/O CH RDY <-- I/O Channel ready, pulled low to lengthen memory cycles
A11 AEN --> Address enable; active high when DMA controls bus
A12 A19 --> Address bit 19
A13 A18 --> Address bit 18
A14 A17 --> Address bit 17
A15 A16 --> Address bit 16
A16 A15 --> Address bit 15
A17 A14 --> Address bit 14
A18 A13 --> Address bit 13
A19 A12 --> Address bit 12
A20 A11 --> Address bit 11
A21 A10 --> Address bit 10
A22 A9 --> Address bit 9
A23 A8 --> Address bit 8
A24 A7 --> Address bit 7
A25 A6 --> Address bit 6
A26 A5 --> Address bit 5
A27 A4 --> Address bit 4
A28 A3 --> Address bit 3
A29 A2 --> Address bit 2
A30 A1 --> Address bit 1
A31 A0 --> Address bit 0
B1 GND Ground
B2 RESET --> Active high to reset or initialize system logic
B3 +5V +5 VDC
B4 IRQ2 <-- Interrupt Request 2
B5 -5VDC -5 VDC
B6 DRQ2 <-- DMA Request 2
B7 -12VDC -12 VDC
B8 /NOWS <-- No WaitState
B9 +12VDC +12 VDC
B10 GND Ground
B11 /SMEMW --> System Memory Write
B12 /SMEMR --> System Memory Read
B13 /IOW --> I/O Write
B14 /IOR --> I/O Read
B15 /DACK3 --> DMA Acknowledge 3
B16 DRQ3 <-- DMA Request 3
B17 /DACK1 --> DMA Acknowledge 1
B18 DRQ1 <-- DMA Request 1
B19 /REFRESH <-> Refresh
B20 CLOCK --> System Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
B21 IRQ7 <-- Interrupt Request 7
B22 IRQ6 <-- Interrupt Request 6
B23 IRQ5 <-- Interrupt Request 5
B24 IRQ4 <-- Interrupt Request 4
B25 IRQ3 <-- Interrupt Request 3
B26 /DACK2 --> DMA Acknowledge 2
B27 T/C --> Terminal count; pulses high when DMA term. count reached
B28 ALE --> Address Latch Enable
B29 +5V +5 VDC
B30 OSC --> High-speed Clock (70 ns, 1431818 MHz, 50% duty cycle)
B31 GND Ground
C1 SBHE <-> System bus high enable (data availble on SD8-15)
C2 LA23 <-> Address bit 23
C3 LA22 <-> Address bit 22
C4 LA21 <-> Address bit 21
C5 LA20 <-> Address bit 20
C6 LA18 <-> Address bit 19
C7 LA17 <-> Address bit 18
C8 LA16 <-> Address bit 17
C9 /MEMR <-> Memory Read (Active on all memory read cycles)
C10 /MEMW <-> Memory Write (Active on all memory write cycles)
C11 SD08 <-> Data bit 8
C12 SD09 <-> Data bit 9
C13 SD10 <-> Data bit 10
C14 SD11 <-> Data bit 11
C15 SD12 <-> Data bit 12
C16 SD13 <-> Data bit 13
C17 SD14 <-> Data bit 14
C18 SD15 <-> Data bit 15
D1 /MEMCS16 <-- Memory 16-bit chip select (1 wait, 16-bit memory cycle)
D2 /IOCS16 <-- I/O 16-bit chip select (1 wait, 16-bit I/O cycle)
D3 IRQ10 <-- Interrupt Request 10
D4 IRQ11 <-- Interrupt Request 11
D5 IRQ12 <-- Interrupt Request 12
D6 IRQ15 <-- Interrupt Request 15
D7 IRQ14 <-- Interrupt Request 14
D8 /DACK0 --> DMA Acknowledge 0
D9 DRQ0 <-- DMA Request 0
D10 /DACK5 --> DMA Acknowledge 5
D11 DRQ5 <-- DMA Request 5
D12 /DACK6 --> DMA Acknowledge 6
D13 DRQ6 <-- DMA Request 6
D14 /DACK7 --> DMA Acknowledge 7
D15 DRQ7 <-- DMA Request 7
D16 +5 V
D17 /MASTER <-- Used with DRQ to gain control of system
D18 GND Ground
Note: Direction is Motherboard relative ISA-Cards.
Note: B8 was /CARD SLCDTD on the XT. Card selected, activated by cards in XT's slot J8
 
 
 
 
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