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PC Card

16-bit bus defined by PCMCIA.

68 PIN ??? MALE (At the controller)
68 PIN ??? FEMALE (At the peripherals)

68 PIN ??? MALE at the controller.
68 PIN ??? FEMALE at the peripherals.

PinMemoryI/O+MemDescription
1 GND GND Ground
2 D3 D3 Data 3
3 D4 D4 Data 4
4 D5 D5 Data 5
5 D6 D6 Data 6
6 D7 D7 Data 7
7 CE1# CE1#
8 A10 A10 Address 10
9 OE# OE# Output Enable
10 A11 A11 Address 11
11 A9 A9 Address 9
12 A8 A8 Address 8
13 A13 A13 Address 13
14 A14 A14 Address 14
15 WE# WE# Write Enable ???
16 READY IREQ#
17 Vcc Vcc Vcc
18 Vpp1 Vpp1 Vpp1
19 A16 A16 Address 16
20 A15 A15 Address 15
21 A12 A12 Address 12
22 A7 A7 Address 7
23 A6 A6 Address 6
24 A5 A5 Address 5
25 A4 A4 Address 4
26 A3 A3 Address 3
27 A2 A2 Address 2
28 A1 A1 Address 1
29 A0 A0 Address 0
30 D0 D0 Data 0
31 D1 D1 Data 1
32 D2 D2 Data 2
33 WP IOIS16#
34 GND GND Ground
35 GND GND Ground
36 CD1# CD1# Card Detect 1
37 D11 D11 Data 11
38 D12 D12 Data 12
39 D13 D13 Data 13
40 D14 D14 Data 14
41 D15 D15 Data 15
42 CE2# CE2#
43 VS1# VS1#
44 RSRVD IORD# Reserved / IORD#
45 RSRVD IOWR# Reserved / IOWR#
46 A17 A17 Address 17
47 A18 A18 Address 18
48 A19 A19 Address 19
49 A20 A20 Address 20
50 A21 A21 Address 21
51 Vcc Vcc Vcc
52 Vpp2 Vpp2 Vpp2
53 A22 A22 Address 22
54 A23 A23 Address 23
55 A24 A24 Address 24
56 A25 A25 Address 25
57 VS2# VS2#
58 RESET RESET Reset
59 WAIT# WAIT#
60 RSRVD INPACK# Reserved / ???
61 REG# REG#
62 BVD2 SPKR# Battery Voltage 2 / Speaker ???
63 BVD1 STSCHG# Battery Voltage 1 / ???
64 D8 D8 Data 8
65 D9 D9 Data 9
66 D10 D10 Data 10
67 CD2# CD2#
68 GND GND Ground
 

CD32 Expansion-port

182 PIN (SAME AS MCA) (At the computer)

UNKNOWN 182 PIN CONNECTOR (SAME AS MCA) at the computer.

PinNameDescriptionComment
1 A31 Address 31 Probably not connected since 68EC020
2 A30 Address 30 Probably not connected since 68EC020
3 A29 Address 29 Probably not connected since 68EC020
4 A28 Address 28 Probably not connected since 68EC020
5 A27 Address 27 Probably not connected since 68EC020
6 A26 Address 26 Probably not connected since 68EC020
7 A25 Address 25 Probably not connected since 68EC020
8 A24 Address 24
9 DGND Data Ground
10 VCC +5 VDC
11 A23 Address 23
12 A22 Address 22
13 A21 Address 21
14 A20 Address 20
15 A19 Address 19
16 A18 Address 18
17 A17 Address 17
18 A16 Address 16
19 DGND Data Ground
20 VCC +5 VDC
21 A15 Address 15
22 A14 Address 14
23 A13 Address 13
24 A12 Address 12
25 A11 Address 11
26 A10 Address 10
27 A9 Address 9
28 A8 Address 8
29 DGND Data Ground
30 VCC +5 VDC
31 A7 Address 7
32 A6 Address 6
33 A5 Address 5
34 A4 Address 4
35 A3 Address 3
36 A2 Address 2
37 A1 Address 1
38 A0 Address 0
39 DGND Data Ground
40 VCC +5 VDC
41 D31 Data 31
42 D30 Data 30
43 D29 Data 29
44 D28 Data 28
45 D27 Data 27
46 D26 Data 26
47 D25 Data 25
48 D24 Data 24
49 DGND Data Ground
50 VCC +5 VDC
51 D23 Data 23
52 D22 Data 22
53 D21 Data 21
54 D20 Data 20
55 D19 Data 19
56 D18 Data 18
57 D17 Data 17
58 D16 Data 16
59 DGND Data Ground
60 VCC +5 VDC
61 D15 Data 15
62 D14 Data 14
63 D13 Data 13
64 D12 Data 12
65 D11 Data 11
66 D10 Data 10
67 D9 Data 9
68 D8 Data 8
69 DGND Data Ground
70 VCC +5 VDC
71 D7 Data 7
72 D6 Data 6
73 D5 Data 5
74 D4 Data 4
75 D3 Data 3
76 D2 Data 2
77 D1 Data 1
78 D0 Data 0
79 DGND Data Ground
80 VCC +5 VDC
81 /IPL2 Interrupt Priority Level 2
82 /IPL1 Interrupt Priority Level 1
83 /IPL0 Interrupt Priority Level 0
84
85 /RST Reset
86 /HALT Halt
87 /ECS ECS??
88 /OCS OCS??
89 SIZE1 Size 1 Indicates number of bytes remaining to transfer
90 SIZE0 Size 0 Indicates number of bytes remaining to transfer
91 /AS Address Strobe
92 /DS Data Strobe
93 /R/W Read/Write
94 /BERR Bus Error
95
96 /AVEC Autovector Req Autovector request during interrupt acknowledge
97 /DSACK1 Data Ack 1 Data trasnfer and size acknowledge
98 /DSACK0 Data Ack 0 Data transfer and size acknowledge
99 CPUCLK_A
100
101 DGND Data Ground
102 VCC +5 VDC
103 FC2 Function Codes 2
104 FC1 Function Codes 1
105 FC0 Function Codes 0
106
107
108
109
110
111 /CPU_BR CPU bus request??
112 /EXP_BG Expansion bus granted??
113 /CPU_BG CPU bus granted??
114 /EXP_BR Expansion bus request??
115
116
117 /PUNT
118 /RESET 68020 RESET
119 /INT2 Interrupt 2 Generate a level 2 interrupt
120 /INT6 Interrupt 2 Generate a level 6 interrupt
121 /KB_CLOCK Keyboard clock
122 /KB_DATA Keyboard data
123 /FIRE0 Fire Button 0??
124 /FIRE1 Fire Button 1??
125 /LED Power On LED ??
126 /ACTIVE Disk active LED
127 /RXD Serial Receive Serial data in
128 /TXD Serial Transmit Serial data out
129 /DKRD Floppy interface (Paula?)
130 /DKWD Floppy interface (Paula?)
131 SYSTEM
132 /DKWE Floppy interface (Paula?)
133 CONFIG_OUT
134
135 DGND Data Ground
136 +12V +12V DC
137 DGND Data Ground
138 +12V +12V DC
139 17MHZ For FMV inteface ??
140 EXT_AUDIO For FMV inteface ??
141 DA_DATA For FMV inteface ??
142 /MUTE For FMV inteface ??
143 DA_LRCLK For FMV inteface ??
144 DA_BCLK For FMV inteface ??
145 DGND Data Ground
146 VCC +5 VDC
147 DR Digital Red
148 DG Digital Green
149 DB Digital Blue
150 DI Digital Intensity
151 /PIXELSW_EXT
152 /PIXELSW
153 /BLANK
154 PIXELCLK Pixelclock For manipulating RBG data
155 DGND Data Ground
156 VCC +5 VDC
157 /CSYNC Composite sync Not buffered.
158 CCK_B Color clock ??
159 /HSYNC Horizontal sync
160 /VSYNC Vertical sync
161 VGND Video ground
162 VGND Video ground
163 AR_EXT Analog Red External
164 AR Analog Red
165 AG_EXT Analog Green External
166 AG Analog Green
167 AB_EXT Analog Blue External
168 AB Analog Blue
169 VGND Video ground
170 VGND Video ground
171 /NTSC
172 /XCLKEN Enable External video clock (Genlock)
173 XCLK External video clock (Genlock)
174 /EXT_VIDEO External Video Disable internal video interfaces
175 DGND Data Ground
176 VCC +5 VDC
177 AGND Audio Ground
178 +12V +12V DC
179 LEFT_EXT Left sound External
180 LEFT Left sound
181 RIGHT_EXT Right sound External
182 RIGHT Right sound
 

Amiga 1200 CPU-port

UNKNOWN (At the computer)

UNKNOWN CONNECTOR at the computer.

PinNameDescription
1 n/c Reserved
2 n/c Reserved
3 n/c Reserved
4 n/c Reserved
5 n/c Reserved
6 n/c Reserved
7 n/c Reserved
8 n/c Reserved
9 GND Ground
10 +5V +5 Volts DC
11 A23 Address 23
12 A22 Address 22
13 A21 Address 21
14 A20 Address 20
15 A19 Address 19
16 A18 Address 18
17 A17 Address 17
18 A16 Address 16
19 GND Ground
20 +5V +5 Volts DC
21 A15 Address 15
22 A14 Address 14
23 A13 Address 13
24 A12 Address 12
25 A11 Address 11
26 A10 Address 10
27 A9 Address 9
28 A8 Address 8
29 GND Ground
30 +5V +5 Volts DC
31 A7 Address 7
32 A6 Address 6
33 A5 Address 5
34 A4 Address 4
35 A3 Address 3
36 A2 Address 2
37 A1 Address 1
38 A0 Address 0
39 GND Ground
40 +5V +5 Volts DC
41 D31 Data 31
42 D30 Data 30
43 D29 Data 29
44 D28 Data 28
45 D27 Data 27
46 D26 Data 26
47 D25 Data 25
48 D24 Data 24
49 GND Ground
50 +5V +5 Volts DC
51 D23 Data 23
52 D22 Data 22
53 D21 Data 21
54 D20 Data 20
55 D19 Data 19
56 D18 Data 18
57 D17 Data 17
58 D16 Data 16
59 GND Ground
60 +5V +5 Volts DC
61 D15 Data 15
62 D14 Data 14
63 D13 Data 13
64 D12 Data 12
65 D11 Data 11
66 D10 Data 10
67 D9 Data 9
68 D8 Data 8
69 GND Ground
70 +5V +5 Volts DC
71 D7 Data 7
72 D6 Data 6
73 D5 Data 5
74 D4 Data 4
75 D3 Data 3
76 D2 Data 2
77 D1 Data 1
78 D0 Data 0
79 GND Ground
80 +5V +5 Volts DC
81 /IPL2
82 /IPL1
83 /IPL0
84 n/c Reserved
85 /RST Reset
86 /HLT Halt
87 n/c Reserved
88 n/c Reserved
89 SIZE1
90 SIZE0
91 /AS Address Strobe
92 /DS Data Strobe
93 R/W Read/Write
94 /BERR Bus Error
95 n/c Reserved
96 /AVEC
97 /DSACK1
98 /DSACK2
99 CPUCKLA
100 ECLOCK EClock pulse
101 GND Ground
102 +5V +5 Volts DC
103 FC2 Processor Status 2
104 FC1 Processor Status 1
105 FC0 Processor Status 0
106 /RMC
107 n/c Reserved
108 n/c Reserved
109 n/c Reserved
110 n/c Reserved
111 /BR Slot specific Bus Arbitration
112 /BG Slot specific Bus Arbitration
113 n/c Reserved
114 /BOSS
115 /FPUCS FPU Chip select
116 /FPUSENSE FPU Sense
117 CCKA
118 /RESET Reset
119 GND Ground
120 +5V +5 Volts DC
121 /NETCS
122 /SPARECS
123 /RTCCS Realtime Clock Chip select
124 /FLASH
125 /REG
126 /CCENA
127 /WAIT
128 /KBRESET Keyboard reset
129 /IORD IO Read
130 /IOWR IO Write
131 /OE Output enable
132 /WE
133 /OVR /DTACK Override
134 XRDY External Ready
135 /ZORRO
136 /WIDE
137 /INT2 Interrupt level 2
138 /INT6 Interrupt level 6
139 GND Ground
140 +5V +5 Volts DC
141 SYSTEM1 System1 Ground
142 SYSTEM0 System0 Ground
143 /xRxD
144 /xTxD
145 /CONFIG OUT
146 AGND Audio Ground
147 ALEFT Audio Left
148 ARIGHT Audio Right
149 +12V +12 Volts DC
150 -12V -12 Volts DC
 

Zorro II

86 PIN EDGE CONNECTOR (At the A2000)

86 PIN EDGE CONNECTOR at the A2000.

None: All of my X's suddenly disappeared. I have now put them back again. I hope the table is correct. Please contact me if not. I don't remember where I found this information.
PinA500A1000A2000A2000BNameDescription
1 X X X X GND Ground
2 X X X X GND Ground
3 X X X X GND Ground
4 X X X X GND Ground
5 X X X X +5V +5 Volts DC
6 X X X X +5V +5 Volts DC
7 X X X X n/c
8 X X X X -5V -5 Volts DC
9 X X n/c
X X 28CLOCK 28MHz Clock
10 X X X X +12V +12 Volts DC
11 X X n/c
X X /COPCFG Configuration Out
12 X X X X CONFIG IN, Grounded
13 X X X X GND Ground
14 X X X X /C3 C3 Clock
15 X X X X CDAC Clock
16 X X X X /C1 C1 Clock
17 X X X X /OVR
18 X X X X RDY Ready
19 X X X X /INT2 Interrupt 2
20 X X /PALOPE
X n/c
X /BOSS
21 X X X X A5 Address 5
22 X X X X /INT6 Interrupt 6
23 X X X X A6 Address 6
24 X X X X A4 Address 4
25 X X X X GND Ground
26 X X X X A3 Address 3
27 X X X X A2 Address 2
28 X X X X A7 Address 7
29 X X X X A1 Address 1
30 X X X X A8 Address 8
31 X X X X FC0 Processor status 0
32 X X X X A9 Address 9
33 X X X X FC1 Processor status 1
34 X X X X A10 Address 10
35 X X X X FC2 Processor status 2
36 X X X X A11 Address 11
37 X X X X GND Ground
38 X X X X A12 Address 12
39 X X X X A13 Address 13
40 X X X X /IPL0
41 X X X X A14 Address 14
42 X X X X /IPL1
43 X X X X A15 Address 15
44 X X X X /IPL2
45 X X X X A16 Address 16
46 X X X X /BEER Bus Error
47 X X X X A17 Address
48 X X X X /VPA
49 X X X X GND Ground
50 X X X X ECLK E Clock
51 X X X X /VMA
52 X X X X A18 Address 18
53 X X X X RST Reset
54 X X X X A19 Address 19
55 X X X X /HLT Halt
56 X X X X A20 Address 20
57 X X X X A22 Address 22
58 X X X X A21 Address 21
59 X X X X A23 Address 23
60 X X /BR
X X /CBR
61 X X X X GND Ground
62 X X X X /BGACK
63 X X X X D15 Data 15
64 X X /BG
X X /CBG
65 X X X X D14 Data 14
66 X X X X /DTACK
67 X X X X D13 Data 13
68 X X X X R/W Read/Write
69 X X X X D12 Data 12
70 X X X X /LDS
71 X X X X D11 Data 11
72 X X X X /UDS
73 X X X X GND Ground
74 X X X X /AS
75 X X X X D0 Data 0
76 X X X X D10 Data 10
77 X X X X D1 Data 1
78 X X X X D9 Data 9
79 X X X X D2 Data 2
80 X X X X D8 Data 8
81 X X X X D3 Data 3
82 X X X X D7 Data 7
83 X X X X D4 Data 4
84 X X X X D6 Data 6
85 X X X X GND Ground
86 X X X X D5 Data 5
 

Miniature Card (Technical)

This section is currently based soly on the Miniature Card specification v1.1.

Signal Descriptions:

A0-A24

Address A0 to A24 are the address bus lines that can address up to 32 Mwords (64 MBytes). The Miniature Card specification does not require the Miniature Card to decode the upper address lines. A 2 Mbyte Miniature Card that does not decode the upper address lines would repeat its address space every 2 Mbytes. Address 0h would access the same physical location as 200000h, 400000h, 600000h, etc.

D0-D15

Data lines D0 through D15 constitute the data bus. The data bus is composed of two bytes, the low byte D[7:0] and the high byte D[15:8].

OE#

OE# indicates that the current bus cycle is a read cycle.

WE#

WE# indicates that the current bus cycle is a write cycle.

VS1#

Voltage Sense 1 signal. The card grounds this signal to indicate it can operate at 3.3 Volts. This signal must either be connected to card GND or left open.

VS2#

Voltage Sense 2 signal. The card grounds this signal to indicate it can operate at x.x Volts (the value to be determined at a later date). This signal must either be connected to card GND or left open.

CEL#

CEL# enables the low byte of the data bus (D[7:0]) on the card. This signal is not used in DRAM cards.

CEH#

CEH# enables the high byte of the data bus (D[15:8]) on the card. This signal is not used in DRAM cards.

RAS#

RAS# strobes in the row address for DRAM cards.

CASL#

CASL# strobes in the low byte column address for DRAM cards.

CASH#

CASH# strobes in the high byte column address for DRAM cards.

RESET#

RESET# controls card initialization. When RESET# transitions from a low state to a high state, the Miniature Card must reset to a predetermined state.

BUSY#

BUSY# is a signal generated by the card to indicate the status of operations within the Miniature Card. When BUSY# is high, the Miniature Card is ready to accept the next command from the host. When BUSY# is low, the Miniature Card is busy and unable to accept some data operations from the host. For example, in Flash Miniature Cards the BUSY# signal is tied to the components RY/BY# signal. However, ROM Miniature Cards would always drive BUSY# high since the host will always be able to read from a ROM Miniature Card.

Vccr

Vccr provides a low current (refresh) voltage supply. Vccr is a feature used by DRAM Miniature Cards to "self-refresh" during "sleep" mode.

SDA

I2C: Serial Data/Address.

SCL

I2C: Serial Clock are used to read the attribute information structure (AIS) from the serial EEPROM in a DRAM card.

CD#

CD# is a grounded interface signal. After a Miniature Card has been inserted, CD# will be forced low. The card detect signal is located in the center of the second row of interface signals, and should be one of the last interface signals to connect to the host. Do not confuse CD# with CINS#. CINS# is an early card detect that is one of the first signals to connect to the host.

BS8#

BS8# is a signal driven by the host to indicate if the data bus is x8 or x16. An 8-bit host must drive BS8# low and tie the high byte data bus D[15:8] to the low byte data bus D[7:0]. A 16-bit host must drive this signal high.

GND

Ground

Vcc

Vcc is used to supply power to the card.

CINS#

CINS# is a grounded signal on the front of the Miniature Card that can be used for early detection of a card insertion. CINS# makes contact on the host when the front of the card is inserted into the socket, before the interface signals connect.

 
 

Miniature Card

Developed by Intel.
Miniature Card is a memory-only expansion card.

UNKNOWN (At the device)
UNKNOWN (At the card)

UNKNOWN CONNECTOR at the device.
UNKNOWN CONNECTOR at the card.

Pin Name Description Dir
1 A18 Address Bus <--
2 A16 Address Bus <--
3 A14 Address Bus <--
4 Vccr Voltage Refresh <--
5 CEH# Card Enable High Byte <--
6 A11 Address Bus <--
7 A9 Address Bus <--
8 A8 Address Bus <--
9 A6 Address Bus <--
10 A5 Address Bus <--
11 A3 Address Bus <--
12 A2 Address Bus <--
13 A0 Address Bus <--
14 RAS# Row Address Strobe <--
15 A24 Address Bus <--
16 A23 Address Bus <--
17 A22 Address Bus <--
18 OE# Output Enable <--
19 D15 Data Bus <->
20 D13 Data Bus <->
21 D12 Data Bus <->
22 D10 Data Bus <->
23 D9 Data Bus <->
24 D0 Data Bus <->
25 D2 Data Bus <->
26 D4 Data Bus <->
27 RFU Reserved for future use  
28 D7 Data Bus <->
29 SDA Serial Data and Address <->
30 SCL Serial Clock <--
31 A19 Address Bus <--
32 A17 Address Bus <--
33 A15 Address Bus <--
34 A13 Address Bus <--
35 A12 Address Bus <--
36 RESET# Reset <--
37 A10 Address Bus <--
38 VS1# Voltage Sense 1 -->
39 A7 Address Bus <--
40 BS8# Bus Size 8 <--
41 A4 Address Bus <--
42 CEL# Card Enable Low Byte <--
43 A1 Address Bus <--
44 CASL# Column Address Strobe Low Byte <--
45 CASH# Column Address Strobe High Byte <--
46 CD# Card Detect -->
47 A21 Address Bus <--
48 BUSY# Ready/Busy -->
49 WE# Write Enable <--
50 D14 Data Bus <->
51 RFU Reserved for future use  
52 D11 Data Bus <->
53 VS2# Voltage Sense 2 -->
54 D8 Data Bus <->
55 D1 Data Bus <->
56 D3 Data Bus <->
57 D5 Data Bus <->
58 D6 Data Bus <->
59 RFU Reserved for future use  
60 A20 Address Bus <--

The following three is separate:

Name Description Dir
GND Ground  
VCC Power  
CINS# Card Insertion -->
Note: Direction is card relative device.
 
 

IndustrialPCI (IPCI)

PCI=Peripheral Component Interconnect.
IndustrialPCI is a a version of PCI adapted for industrial and/or embedded applications.

The IPCI connector has three parts:

  • Optional 60 pin PCI 64 bit extension (Top)
  • Mandatory 120 pin PCI 32 bit (Middle)
  • Optional 60 pin Custom I/O (Bottom)

UNKNOWN (At the backplane)
UNKNOWN (At the device (card))

UNKNOWN CONNECTOR at the backplane.
UNKNOWN CONNECTOR at the device (card).

System Slot (Middle)

PinNameDescriptionNote
A1 +3,3V +3.3 VDC
A2 AD2 Address 2
A3 AD6 Address 6
A4 GND Ground
A5 AD10 Address 10
A6 AD13 Address 13
A7 GND Ground
A8 SDONE Snoop Done 1
A9 GND Ground
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18
A12 GND Ground
A13 +5V +5 VDC
A14 AD24 Address 24
A15 AD27 Address 27
A16 GND Ground
A17 REQ2 Request 2 1
A18 GND Ground
A19 CLK1 33 or 66 MHz Clock
A20 CLK2
A21 GND Ground
A22 CLK3
A23 CLK4
A24 +3,3V +3.3 VDC
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3
B3 +5V +5 VDC
B4 AD8 Address 8
B5 +3,3V +3.3 VDC
B6 AD14 Address 14
B7 PAR Parity
B8 +3,3V +3.3 VDC
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2
B11 V(I/O) +3.3 or +5 VDC
B12 AD21 Address 21
B13 +3,3V +3.3 VDC
B14 V(I/O) +3.3 or +5 VDC
B15 AD28 Address 28
B16 AD31 Address 31
B17 +3,3V +3.3 VDC
B18 GNT3 Grant 3
B19 RST# Reset
B20 NMI# Non Maskable Interrupt
B21 X6 Reserved (6)
B22 +5V +5 VDC :
B23 RSTIN# 2
B24 USB+ Universal Serial Bus (USB)(+)
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground
C3 AD7 Address 7
C4 AD9 Address 9
C5 AD11 Address 11
C6 GND Ground
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground
C11 AD19 Address 19
C12 AD22 Address 22
C13 GND Ground
C14 AD25 Address 25
C15 GND Ground
C16 X1 Reserved (1)
C17 GNT2 Grant 2
C18 REQ4 Request 4 1
C19 SLEEP#/SDAT Sleep/Serial Data (I2C) 3
C20 X4 Reserved (4)
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC
C24 USB- Universal Serial Bus (USB)(-)
D1 AD0 Address 0
D2 AD4 Address 4
D3 C/BE0# Command, Byte Enable 0
D4 +3,3V +3.3 VDC
D5 AD12 Address 12
D6 AD15 Address 15
D7 V(I/O) +3.3 or +5 VDC
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16
D11 AD20 Address 20
D12 +5V +5 VDC
D13 +5V +5 VDC
D14 AD26 Address 26
D15 AD29 Address 29
D16 REQ1 Request 1 1
D17 REQ3 Request 3 1
D18 V(I/O) +3.3 or +5 VDC
D19 X2 Reserved (2)
D20 X5 Reserved (5)
D21 +3,3V +3.3 VDC
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)
E1 AD1 Address 1
E2 AD5 Address 5
E3 GND Ground
E4 M66EN Enable 66Mhz PCI-bus
E5 GND Ground
E6 C/BE1# Command, Byte Enable 1
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC
E9 IRDY# Initatior Ready 1
E10 AD17 Address 17
E11 GND Ground
E12 AD23 Address 23
E13 C/BE3# Command, Byte Enable 3
E14 GND Ground
E15 AD30 Address 30
E16 GNT1 Grant 1
E17 +5V +5 VDC
E18 GNT4 Grant 4
E19 X3 Reserved (3)
E20 GND Ground
E21 INTC# Interrupt C 1
E22 -12V -12 VDC
E23 +12V +12 VDC
E24 VBATT

1 = Pullup resistor of 2,7 kW on the System Slot (CPU).
2 = Pullup resistor of 330 W on the System Slot (CPU).
3 = Pullup resistor of 4,7 kW, if not supported by the System Slot (CPU).

Module Bus Slot (Middle)

PinNameDescriptionNote
A1 +3,3V +3.3 VDC
A2 AD2 Address 2
A3 AD6 Address 6
A4 GND Ground
A5 AD10 Address 10
A6 AD13 Address 13
A7 GND Ground
A8 SDONE Snoop Done 1
A9 GND Ground
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18
A12 GND Ground
A13 +5V +5 VDC
A14 AD24 Address 24
A15 AD27 Address 27
A16 GND Ground
A17 REQ2 Request 2 1
A18 CLKM
A19 CLK1 33 or 66 MHz Clock
A20 CLK2
A21 GND Ground
A22 CLK3
A23 CLK4
A24 +3,3V +3.3 VDC
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3
B3 +5V +5 VDC
B4 AD8 Address 8
B5 +3,3V +3.3 VDC
B6 AD14 Address 14
B7 PAR Parity
B8 +3,3V +3.3 VDC
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2
B11 V(I/O) +3.3 or +5 VDC
B12 AD21 Address 21
B13 +3,3V +3.3 VDC
B14 V(I/O) +3.3 or +5 VDC
B15 AD28 Address 28
B16 AD31 Address 31
B17 +3,3V +3.3 VDC
B18 GNT3 Grant 3
B19 RST# Reset
B20 NMI# Non Maskable Interrupt
B21 X6 Reserved (6)
B22 +5V +5 VDC :
B23 RSTIN#
B24 USB+ Universal Serial Bus (USB)(+)
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground
C3 AD7 Address 7
C4 AD9 Address 9
C5 AD11 Address 11
C6 GND Ground
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground
C11 AD19 Address 19
C12 AD22 Address 22
C13 GND Ground
C14 AD25 Address 25
C15 GND Ground
C16 X1 Reserved (1)
C17 GNT2 Grant 2
C18 REQ4 Request 4 1
C19 SLEEP#/SDAT Sleep/Serial Data (I2C)
C20 X4 Reserved (4)
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC
C24 USB- Universal Serial Bus (USB)(-)
D1 AD0 Address 0
D2 AD4 Address 4
D3 C/BE0# Command, Byte Enable 0
D4 +3,3V +3.3 VDC
D5 AD12 Address 12
D6 AD15 Address 15
D7 V(I/O) +3.3 or +5 VDC
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16
D11 AD20 Address 20
D12 +5V +5 VDC
D13 +5V +5 VDC
D14 AD26 Address 26
D15 AD29 Address 29
D16 REQ1 Request 1 1
D17 REQ3 Request 3 1
D18 V(I/O) +3.3 or +5 VDC
D19 X2 Reserved (2)
D20 X5 Reserved (5)
D21 +3,3V +3.3 VDC
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)
E1 AD1 Address 1
E2 AD5 Address 5
E3 GND Ground
E4 M66EN Enable 66Mhz PCI-bus
E5 GND Ground
E6 C/BE1# Command, Byte Enable 1
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC
E9 IRDY# Initatior Ready 1
E10 AD17 Address 17
E11 GND Ground
E12 AD23 Address 23
E13 C/BE3# Command, Byte Enable 3
E14 GND Ground
E15 AD30 Address 30
E16 GNT1 Grant 1
E17 +5V +5 VDC
E18 GNT4 Grant 4
E19 X3 Reserved (3)
E20 GND Ground
E21 INTC# Interrupt C 1
E22 -12V -12 VDC
E23 +12V +12 VDC
E24 VBATT

1 = Pullup resistor of 2,7 kW on the System Slot (CPU).

Card Slot (Middle)

PinNameDescriptionNote
A1 +3,3V +3.3 VDC
A2 AD2 Address 2
A3 AD6 Address 6
A4 GND Ground
A5 AD10 Address 10
A6 AD13 Address 13
A7 GND Ground
A8 SDONE Snoop Done 1
A9 GND Ground
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18
A12 GND Ground
A13 +5V +5 VDC
A14 AD24 Address 24
A15 AD27 Address 27
A16 GND Ground
A17 IDSEL0 IDSEL0 1
A18 GND Ground
A19 CLK1 33 or 66 MHz Clock
A20 GND Ground
A21 GND Ground
A22 GND Ground
A23 GND Ground
A24 +3,3V +3.3 VDC
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3
B3 +5V +5 VDC
B4 AD8 Address 8
B5 +3,3V +3.3 VDC
B6 AD14 Address 14
B7 PAR Parity
B8 +3,3V +3.3 VDC
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2
B11 V(I/O) +3.3 or +5 VDC
B12 AD21 Address 21
B13 +3,3V +3.3 VDC
B14 V(I/O) +3.3 or +5 VDC
B15 AD28 Address 28
B16 AD31 Address 31
B17 +3,3V +3.3 VDC
B18 GND Ground
B19 RST# Reset
B20 NMI# Non Maskable Interrupt
B21 X6 Reserved (6)
B22 +5V +5 VDC :
B23 RSTIN#
B24 USB+ Universal Serial Bus (USB)(+)
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground
C3 AD7 Address 7
C4 AD9 Address 9
C5 AD11 Address 11
C6 GND Ground
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground
C11 AD19 Address 19
C12 AD22 Address 22
C13 GND Ground
C14 AD25 Address 25
C15 GND Ground
C16 X1 Reserved (1)
C17 IDSEL1 Initialization Device Select 1
C18 GND Ground
C19 SLEEP#/SDAT Sleep/Serial Data (I2C)
C20 X4 Reserved (4)
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC
C24 USB- Universal Serial Bus (USB)(-)
D1 AD0 Address 0
D2 AD4 Address 4
D3 C/BE0# Command, Byte Enable 0
D4 +3,3V +3.3 VDC
D5 AD12 Address 12
D6 AD15 Address 15
D7 V(I/O) +3.3 or +5 VDC
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16
D11 AD20 Address 20
D12 +5V +5 VDC
D13 +5V +5 VDC
D14 AD26 Address 26
D15 AD29 Address 29
D16 REQ1 Request 1 1
D17 IDSEL2 Initialization Device Select 2
D18 V(I/O) +3.3 or +5 VDC
D19 X2 Reserved (2)
D20 X5 Reserved (5)
D21 +3,3V +3.3 VDC
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)
E1 AD1 Address 1
E2 AD5 Address 5
E3 GND Ground
E4 M66EN Enable 66Mhz PCI-bus
E5 GND Ground
E6 C/BE1# Command, Byte Enable 1
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC
E9 IRDY# Initatior Ready 1
E10 AD17 Address 17
E11 GND Ground
E12 AD23 Address 23
E13 C/BE3# Command, Byte Enable 3
E14 GND Ground
E15 AD30 Address 30
E16 GNT1 Grant 1
E17 +5V +5 VDC
E18 GNT4 Grant 4
E19 X3 Reserved (3)
E20 GND Ground
E21 INTC# Interrupt C 1
E22 -12V -12 VDC
E23 +12V +12 VDC
E24 VBATT

1 = Pullup resistor of 2,7 kW on the System Slot (CPU).

64-bit PCI (Top)

PinNameDescriptionNote
A1 GND Ground
A2 X10 Reserved (10)
A3 AD35 Address 35 2
A4 AD38 Address 38 2
A5 AD42 Address 42 2
A6 V(I/O) +3.3 or +5 VDC
A7 V(I/O) +3.3 or +5 VDC
A8 AD52 Address 52 2
A9 AD56 Address 56 2
A10 AD60 Address 60 2
A11 AD63 Address 63 2
A12 GND Ground
B1 X7 Reserved (7)
B2 GND Ground
B3 AD36 Address 36 2
B4 AD39 Address 39 2
B5 AD43 Address 43 2
B6 AD46 Address 46 2
B7 AD49 Address 49 2
B8 AD53 Address 53 2
B9 AD57 Address 57 2
B10 AD61 Address 61 2
B11 GND Ground
B12 C/BE6# Command, Byte Enable 6 2
C1 X8 Reserved (8)
C2 AD32 Address 32 2
C3 GND Ground
C4 AD40 Address 40 2
C5 AD44 Address 44 2
C6 GND Ground
C7 GND Ground
C8 AD54 Address 54 2
C9 AD58 Address 58 2
C10 GND Ground
C11 PAR64 Parity 64 ??? 2
C12 C/BE7# Command, Byte Enable 7 2
D1 X9 Reserved (9)
D2 AD33 Address 33 2
D3 AD37 Address 37 2
D4 GND Ground
D5 AD45 Address 45 2
D6 AD47 Address 47 2
D7 AD50 Address 50 2
D8 AD55 Address 55 2
D9 GND Ground
D10 AD62 Address 62 2
D11 C/BE4# Command, Byte Enable 4 2
D12 X11 Reserved (11)
E1 GND Ground
E2 AD34 Address 34 2
E3 V(I/O) +3.3 or +5 VDC
E4 AD41 Address 41 2
E5 GND Ground
E6 AD48 Address 48 2
E7 AD51 Address 51 2
E8 GND Ground
E9 AD59 Address 59 2
E10 V(I/O) +3.3 or +5 VDC
E11 C/BE5# Command, Byte Enable 5 2
E12 X12 Reserved (12)

2 = Pullup resistor of 2,7 kW (5V bus system) or 8,2 kW (3,3V bus system) on the backplane.

ISA96/AT96 (Bottom)

PinNameDescriptionNote
A1 RSTDRV
A2 IRQ9 Interrupt 9
A3 SD11 Data 11
A4 SD9 Data 9
A5 IOCHRDY 1
A6 IOW# I/O Write
A7 SA15 Address 15
A8 CLK Clock
A9 SA10 Address 10
A10 SA7 Address 7
A11 T/C
A12 SA2 Address 2
B1 SD15 Data 15
B2 SD13 Data 13
B3 SD3 Data 3
B4 SD1 Data 1
B5 SMEMW# System Memory Write
B6 SA18 Address 18
B7 SA14 Address 14
B8 DACK6# DMA Acknowledge 6
B9 SA9 Address 9
B10 IRQ3 Interrupt 3
B11 IOCS16# I/O 16-bit chip select 1
B12 SA1 Address 1
C1 SD7 Data 7
C2 SD5 Data 5
C3 SD10 Data 10
C4 SD8 Data 8
C5 AEN Address Enable
C6 IOR# I/O Read
C7 SA13 Address 13
C8 SA11 Address 11
C9 IRQ5 Interrupt 5
C10 SA6 Address 6
C11 SA4 Address 4
C12 IRQ11 Interrupt 11
D1 SD14 Data 14
D2 SD12 Data 12
D3 SD2 Data 2
D4 SD0 Data 0
D5 SMEMR# System Memory Read
D6 SA17 Address 17
D7 REF#
D8 IRQ7 Interrupt 7
D9 SA8 Address 8
D10 MCS16# 1
D11 BALE
D12 SA0 Address 0
E1 SD6 Data 6
E2 SD4 Data 4
E3 0WS 1
E4 SBHE#
E5 SA19 Address 19
E6 SA16 Address 16
E7 SA12 Address 12
E8 DRQ6 DMA Request 6
E9 IRQ4 Interrupt 4
E10 SA5 Address 5
E11 SA3 Address 3
E12 IRQ10 Interrupt 10

1 = Pullup resistor must be integrated into the System Slot (CPU).

VMEbus (Bottom)

PinNameDescription
A1 D0 Data 0
A2 D2 Data 2
A3 D12 Data 12
A4 D7 Data 7
A5 DS1#
A6 BR3#
A7 AM1
A8 AM3
A9 IACKOUT#
A10 A14 Address 14
A11 A12 Address 12
A12 A10 Address 10
B1 BBSY#
B2 D10 Data 10
B3 D5 Data 5
B4 D15 Data 15
B5 SYSRES#
B6 A23 Address 23
B7 A21 Address 21
B8 A19 Address 19
B9 A16 Address 16
B10 A6 Address 6
B11 A4 Address 4
B12 A2 Address 2
C1 D8 Data 8
C2 D3 Data 3
C3 D13 Data 13
C4 SYSCLK
C5 DS0#
C6 DTACK#
C7 AS#
C8 IACK#
C9 AM4
C10 A13 Address 13
C11 A11 Address 11
C12 A9 Address 9
D1 D1 Data 1
D2 D11 Data 11
D3 D6 Data 6
D4 BG3OUT#
D5 WR# Write
D6 AM0
D7 AM2
D8 A18 Address 18
D9 A15 Address 15
D10 A5 Address 5
D11 A3 Address 3
D12 A1 Address 1
E1 D9 Data 9
E2 D4 Data 4
E3 D14 Data 14
E4 BERR# Bus Error
E5 AM5
E6 A22 Address 22
E7 A20 Address 20
E8 A17 Address 17
E9 A7 Address 7
E10 IRQ5# Interrupt 5
E11 IRQ3# Interrupt 3
E12 A8 Address 8

ECB (Bottom)

PinNameDescription
A1 D5 Data 5
A2 D2 Data 2
A3 A4 Data 4
A4 A7 Address 7
A5 BAI
A6 2F
A7 A10 Address 10
A8 INT#
A9 VCMOS
A10 PWRCLR#
A11 A13 Address 13
A12 RESET# Reset
B1 D0 Data 0
B2 D4 Data 4
B3 A1 Address 1
B4 WAIT#
B5 A17 Address 17
B6 IEO
B7 n/c Not connected
B8 DMARDY
B9 RD# Read
B10 IORQ#
B11 ?
B12 n/c Not connected
C1 D6 Data 6
C2 A0 Address 0
C3 A5 Address 5
C4 A16 Address 16
C5 A18 Address 18
C6 BAO
C7 M1#
C8 WR#
C9 n
C10 A12 Address 12
C11 A9 Address 9
C12 n/c Not connected
D1 D7 Data 7
D2 A2 Address 2
D3 A8 Address 8
D4 BUSRQ#
D5 A19 Address 19
D6 A11 Address 11
D7 NMI# Non Maskable Interrupt
D8 PF
D9 HALT#
D10 RFSH#
D11 MRQ#
D12 n/c Not connected
E1 D3 Data 3
E2 A3 Address 3
E3 A6 Address 6
E4 IEI
E5 D1 Data 1
E6 A14 Address 14
E7 n/c Not connected
E8 n/c Not connected
E9 DESLCT#
E10 A15 Address 15
E11 BUSAK#
E12 n/c Not connected

SMP16 (Bottom)

PinNameDescription
A1 NMI# Non Maskable Interrupt
A2 IRQ0# Interrupt 0
A3 D11 Data 11
A4 D9 Data 9
A5 RDYIN
A6 IOW#
A7 A15 Address 15
A8 CLK
A9 A10 Address 10
A10 A7 Address 7
A11 TC/EOP#
A12 A2 Address 2
B1 D15 Data 15
B2 D13 Data 13
B3 D3 Data 3
B4 D1 Data 1
B5 MEMW#
B6 A18 Address 18
B7 A14 Address 14
B8 DACKx#
B9 A9 Address 9
B10 IRQ3# Interrupt 3
B11 IOCS16#
B12 A1 Address 1
C1 D7 Data 7
C2 D5 Data 5
C3 D10 Data 10
C4 D8 Data 8
C5 BUSEN
C6 IOR#
C7 A13 Address 13
C8 A11 Address 11
C9 IRQ1# Interrupt 1
C10 A6 Address 6
C11 A4 Address 4
C12 IRQ4# Interrupt 4
D1 D14 Data 14
D2 D12 Data 12
D3 D2 Data 2
D4 D0 Data 0
D5 MEMR#
D6 A17 Address 17
D7 INTA#
D8 INT#
D9 A8 Address 8
D10 MECS16#
D11 ALE
D12 A0 Address 0
E1 D6 Data 6
E2 D4 Data 4
E3 MMIO#
E4 BHEN
E5 A19 Address 19
E6 A16 Address 16
E7 A12 Address 12
E8 DRQx#
E9 IRQ2# Interrupt 2
E10 A5 Address 5
E11 A3 Address 3
E12 IRQ5# Interrupt 5

Floppy/EIDE (Bottom)

PinNameDescription
A1 FDSEL1 Floppy Select 1
A2 FDSEL0 Floppy Select 0
A3 FDME1 Floppy ?
A4 DIR Floppy Direction
A5 STEP Floppy Step
A6 WRDATA Floppy Write Data
A7 WE Floppy Write?
A8 TRK0 Floppy Track 0
A9 WP Floppy Write?
A10 RDDATA Floppy ?
A11 HDSEL Floppy HD Select
A12 DSKCHG Floppy DiskChange
B1 DRVDEN1 ?
B2 DRVDEN0 ?
B3 IDECS3P# IDE ?
B4 IDEA2 IDE ?
B5 IDEIRQS IDE ?
B6 IDEPUS IDE ?
B7 IDEDRQP IDE ?
B8 IDED14 IDE Data 14
B9 IDED8 IDE Data 8
B10 IDED6 IDE Data 6
B11 IDED11 IDE Data 11
B12 IDED3 IDE Data 3
C1 FDME0 Floppy Me?
C2 INDX Floppy Index
C3 IDECS3S# IDE ?
C4 IDEA0 IDE ?
C5 IDEDAKS# IDE ?
C6 IDEIOR# IDE ?
C7 IDEDRQS IDE ?
C8 IDED1 IDE Data 1
C9 #IDERST IDE ?
C10 IDED10 IDE Data 10
C11 IDED4 IDE Data 4
C12 IDED2 IDE Data 2
D1 IDELEDS# IDE LED ?
D2 IDELEDP# IDE LED ?
D3 IDECS1S# IDE ?
D4 IDEIRQP IDE ?
D5 IDEPUP IDE Pull Up ?
D6 IDEIOW# IDE ?
D7 IDED15 IDE Data 15
D8 IDED13 IDE Data 13
D9 IDED7 IDE Data 7
D10 GND Ground
D11 GND Ground
D12 GND Ground
E1 GND Ground
E2 GND Ground
E3 IDECS1P# IDE ?
E4 IDEA1 IDE ?
E5 IDEDAKP# IDE ?
E6 IDEIORDY IDE ?
E7 IDED0 IDE Data 0
E8 IDED12 IDE Data 12
E9 IDED9 IDE Data 9
E10 IDED5 IDE Data 5
E11 GND Ground
E12 GND Ground

SCSI (Bottom)

PinNameDescription
A1 TERM
A2 GND Ground
A3 I/O#
A4 REQ#
A5 ATN#
A6 D8 Data 8
A7 D9 Data 9
A8 D10 Data 10
A9 D2 Data 2
A10 D4 Data 4
A11 DP0
A12 GND Ground
B1 TERM
B2 GND Ground
B3 GND Ground
B4 GND Ground
B5 GND Ground
B6 GND Ground
B7 GND Ground
B8 GND Ground
B9 GND Ground
B10 GND Ground
B11 GND Ground
B12 GND Ground
C1 TERM
C2 GND Ground
C3 C/D#
C4 MSG#
C5 ACK#
C6 D12 Data 12
C7 DP1 Data P1
C8 D13 Data 13
C9 D1 Data 1
C10 D5 Data 5
C11 D7 Data 7
C12 GND Ground
D1 TERM
D2 GND Ground
D3 GND Ground
D4 GND Ground
D5 GND Ground
D6 GND Ground
D7 GND Ground
D8 GND Ground
D9 GND Ground
D10 GND Ground
D11 GND Ground
D12 GND Ground
E1 TERM
E2 GND Ground
E3 SEL#
E4 RST#
E5 BSY#
E6 D14 Data 14
E7 D15 Data 15
E8 D11 Data 11
E9 D0 Data 0
E10 D3 Data 3
E11 D6 Data 6
E12 GND Ground
 

VESA LocalBus (VLB)

VLB=VESA Local Bus.
VESA=Video Electronics Standards Association.

58 PIN EDGE CONNECTOR MALE (At the card)
58 PIN EDGE CONNECTOR FEMALE (At the computer)

58 PIN EDGE CONNECTOR MALE at the card.
58 PIN EDGE CONNECTOR FEMALE at the computer.

PinNameDescription
A1 D1 Data 1
A2 D3 Data 3
A3 GND Ground
A4 D5 Data 5
A5 D7 Data 7
A6 D9 Data 9
A7 D11 Data 11
A8 D13 Data 13
A9 D15 Data 15
A10 GND Ground
A11 D17 Data 17
A12 Vcc +5 VDC
A13 D19 Data 19
A14 D21 Data 21
A15 D23 Data 23
A16 D25 Data 25
A17 GND Ground
A18 D27 Data 27
A19 D29 Data 2
A20 D31 Data 31
A21 A30 Address 30
A22 A28 Address 28
A23 A26 Address 26
A24 GND Ground
A25 A24 Address 24
A26 A22 Address 22
A27 VCC +5 VDC
A28 A20 Address 20
A29 A18 Address 18
A30 A16 Address 16
A31 A14 Address 14
A32 A12 Address 12
A33 A10 Address 10
A34 A8 Address 8
A35 GND Ground
A36 A6 Address 6
A37 A4 Address 4
A38 WBACK# Write Back
A39 BE0# Byte Enable 0
A40 VCC +5 VDC
A41 BE1# Byte Enable 1
A42 BE2# Byte Enable 2
A43 GND Ground
A44 BE3# Byte Enable 3
A45 ADS# Address Strobe
A48 LRDY# Local Ready
A49 LDEV Local Device
A50 LREQ Local Request
A51 GND Ground
A52 LGNT Local Grant
A53 VCC +5 VDC
A54 ID2 Identification 2
A55 ID3 Identification 3
A56 ID4 Identification 4
A57 LKEN#
A58 LEADS# Local Enable Address Strobe
B1 D0 Data 0
B2 D2 Data 2
B3 D4 Data 4
B4 D6 Data 6
B5 D8 Data 8
B6 GND Ground
B7 D10 Data 10
B8 D12 Data 12
B9 VCC +5 VDC
B10 D14 Data 14
B11 D16 Data 16
B12 D18 Data 18
B13 D20 Data 20
B14 GND Ground
B15 D22 Data 22
B16 D24 Data 24
B17 D26 Data 26
B18 D28 Data 28
B19 D30 Data 30
B20 VCC +5 VDC
B21 A31 Address 31
B22 GND Ground
B23 A29 Address 29
B24 A27 Address 27
B25 A25 Address 25
B26 A23 Address 23
B27 A21 Address 21
B28 A19 Address 19
B29 GND Ground
B30 A17 Address 17
B31 A15 Address 15
B32 VCC +5 VDC
B33 A13 Address 13
B34 A11 Address 11
B35 A9 Address 9
B36 A7 Address 7
B37 A5 Address 5
B38 GND Ground
B39 A3 Address 3
B40 A2 Address 2
B41 n/c Not connected
B42 RESET# Reset
B43 DC# Data/Command
B44 M/IO# Memory/IO
B45 W/R# Write/Read
B48 RDYRTN# Ready Return
B49 GND Ground
B50 IRQ9 Interrupt 9
B51 BRDY# Burst Ready
B52 BLAST# Burst Last
B53 ID0 Identification 0
B54 ID1 Identification 1
B55 GND Ground
B56 LCLK Local Clock
B57 VCC +5 VDC
B58 LBS16# Local Bus Size 16
 

PCI (Technical)

This section is currently based soly on the work by Mark Sokos.

This file is not intended to be a thorough coverage of the PCI standard. It is for informational purposes only, and is intended to give designers and hobbyists an overview of the bus so that they might be able to design their own PCI cards. Thus, I/O operations are explained in the most detail, while memory operations, which will usually not be dealt with by an I/O card, are only briefly explained. Hobbyists are also warned that, due to the higher clock speeds involved, PCI cards are more difficult to design than ISA cards or cards for other slower busses. Many companies are now making PCI prototyping cards, and, for those fortunate enough to have access to FPGA programmers, companies like Xilinx are offering PCI compliant designs which you can use as a starting point for your own projects.

For a copy of the full PCI standard, contact:

PCI Special Interest Group (SIG)
PO Box 14070
Portland, OR 97214
1-800-433-5177
1-503-797-4207

Signal Descriptions:

AD(x)

Address/Data Lines.

CLK

Clock. 33 MHz maximum.

C/BE(x)

Command, Byte Enable.

FRAME

Used to indicate whether the cycle is an address phase or or a data phase.

DEVSEL

Device Select.

IDSEL

Initialization Device Select

INT(x)

Interrupt

IRDY

Initiator Ready

LOCK

Used to manage resource locks on the PCI bus.

REQ

Request. Requests a PCI transfer.

GNT

Grant. indicates that permission to use PCI is granted.

PAR

Parity. Used for AD0-31 and C/BE0-3.

PERR

Parity Error.

RST

Reset.

SBO

Snoop Backoff.

SDONE

Snoop Done.

SERR

System Error. Indicates an address parity error for special cycles or a system error.

STOP

Asserted by Target. Requests the master to stop the current transfer cycle.

TCK

Test Clock

TDI

Test Data Input

TDO

Test Data Output

TMS

Test Mode Select

TRDY

Target Ready

TRST

Test Logic Reset

The PCI bus treats all transfers as a burst operation. Each cycle begins with an address phase followed by one or more data phases. Data phases may repeat indefinately, but are limited by a timer that defines the maximum amount of time that the PCI device may control the bus. This timer is set by the CPU as part of the configuration space. Each device has its own timer (see the Latency Timer in the configuration space).

The same lines are used for address and data. The command lines are also used for byte enable lines. This is done to reduce the overall number of pins on the PCI connector.

The Command lines (C/BE3 to C/BE0) indicate the type of bus transfer during the address phase.

C/BECommand Type
0000 Interrupt Acknowledge
0001 Special Cycle
0010 I/O Read
0011 I/O Write
0100 reserved
0101 reserved
0110 Memory Read
0111 Memory Write
1000 reserved
1001 reserved
1010 Configuration Read
1011 Configuration Write
1100 Multiple Memory Read
1101 Dual Address Cycle
1110 Memory-Read Line
1111 Memory Write and Invalidate

The three basic types of transfers are I/O, Memory, and Configuration.

PCI timing diagrams:

            ___     ___     ___     ___     ___     ___
CLK     ___|   |___|   |___|   |___|   |___|   |___|   |___
        _______                                   _________
FRAME          |_________________________________|
                ______  _______  ______  ______  ______
AD      ----------
                Address  Data1    Data2   Data3   Data4
                ______  _______________________________
C/BE    ----------
                Command   Byte Enable Signals
         ____________                                   ___
IRDY                 |_________________________________|
         _____________                                  ___
TRDY                  |________________________________|
         ______________                                 ___
DEVSEL                 |_______________________________|

PCI transfer cycle, 4 data phases, no wait states. Data is transferred on the rising edge of CLK.

                         [1]              [2]        [3]
            ___     ___     ___     ___     ___     ___     ___     ___
CLK     ___|   |___|   |___|   |___|   |___|   |___|   |___|   |___|   |__
        _______                                                  _________
FRAME          |________________________________________________|
                                   A               B               C
                ______           ______________  ______  _____________
AD      -------------------
                Address           Data1           Data2   Data3
                ______  ______________________________________________
C/BE    ----------
                Command   Byte Enable Signals
                                                         Wait
         ____________                                    _____         ___
IRDY                 |__________________________________|     |_______|
                        Wait            Wait
         ______________________         ______                         ___
TRDY                           |_______|      |_______________________|
         ______________                                                ___
DEVSEL                 |______________________________________________|

PCI transfer cycle, with wait states. Data is transferred on the rising edge of CLK at points labled A, B, and C.

Bus Cycles:

Interrupt Acknowledge (0000)

The interrupt controller automatically recognizes and reacts to the INTA (interrupt acknowledge) command. In the data phase, it transfers the interrupt vector to the AD lines.

Special Cycle (0001)

AD15-AD0Description
0x0000 Processor Shutdown
0x0001 Processor Halt
0x0002 x86 Specific Code
0x0003 to 0xFFFF Reserved

I/O Read (0010) and I/O Write (0011)

Input/Output device read or write operation. The AD lines contain a byte address (AD0 and AD1 must be decoded). PCI I/O ports may be 8 or 16 bits. PCI allows 32 bits of address space. On IBM compatible machines, the Intel CPU is limited to 16 bits of I/O space, which is further limited by some ISA cards that may also be installed in the machine (many ISA cards only decode the lower 10 bits of address space, and thus mirror themselves throughout the 16 bit I/O space). This limit assumes that the machine supports ISA or EISA slots in addition to PCI slots.

The PCI configuration space may also be accessed through I/O ports 0x0CF8 (Address) and 0x0CFC (Data). The address port must be written first.

Memory Read (0110) and Memory Write (0111)

A read or write to the system memory space. The AD lines contain a doubleword address. AD0 and AD1 do not need to be decoded. The Byte Enable lines (C/BE) indicate which bytes are valid.

Configuration Read (1010) and Configuration Write (1011)

A read or write to the PCI device configuration space, which is 256 bytes in length. It is accessed in doubleword units. AD0 and AD1 contain 0, AD2-7 contain the doubleword address, AD8-10 are used for selecting the addressed unit a the malfunction unit, and the remaining AD lines are not used.

Address     Bit 32      16   15           0
00          Unit ID        | Manufacturer ID
04          Status         | Command
08          Class Code               | Revision
0C          BIST  | Header | Latency | CLS
10-24            Base Address Register
28          Reserved
2C          Reserved
30          Expansion ROM Base Address
34          Reserved
38          Reserved
3C          MaxLat|MnGNT   | INT-pin | INT-line
40-FF       available for PCI unit

Multiple Memory Read (1100)

This is an extension of the memory read bus cycle. It is used to read large blocks of memory without caching, which is beneficial for long sequential memory accesses.

Dual Address Cycle (1101)

Two address cycles are necessary when a 64 bit address is used, but only a 32 bit physical address exists. The least significant portion of the address is placed on the AD lines first, followed by the most significant 32 bits. The second address cycle also contains the command for the type of transfer (I/O, Memory, etc). The PCI bus supports a 64 bit I/O address space, although this is not available on Intel based PCs due to limitations of the CPU.

Memory-Read Line (1110)

This cycle is used to read in more than two 32 bit data blocks, typically up to the end of a cache line. It is more effecient than normal memory read bursts for a long series of sequential memory accesses.

Memory Write and Invalidate (1111)

This indicates that a minimum of one cache line is to be transferred. This allows main memory to be updated, saving a cache write-back cycle.

Bus Arbitration:

This section is under construction.

PCI Bios:

This section is under construction.

 

EISA (Technical)

This section is currently based soly on the work by Mark Sokos.

This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists and ametuers can design their own EISA compatible cards.

It is not intended to provide complete coverage of the EISA standard.

EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the ISA architecture, which is a standardized version of the bus originally developed by IBM for their PC computers. EISA is upwardly compatible, which means that cards originally designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the 16 bit bus (referred to as the AT bus, and also as the ISA bus), will work in an EISA slot. EISA specific cards will not work in an AT or an XT slot.

The EISA connector uses multiple rows of connectors. The upper row is the same as a regular ISA slot, and the lower row contains the EISA extension. The slot is keyed so that ISA cards cannot be inserted to the point where they connet with the EISA signals.

Signal Descriptions

+5, -5, +12, -12

Power supplies. -5 is often not implimented.

AEN

Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from responding to the I/O command lines during a DMA transfer.

BALE

Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should latch the LA bus on the falling edge of BALE.

BCLK

Bus Clock, 33% Duty Cycle. Frequency Varies. 8.33 MHz is specified as the maximum, but many systems allow this clock to be set to 10 MHz and higher.

BE(x)

Byte Enable. Indicates to the slave device which bytes on the data bus contain valid data. A 16 bit transfer would assert BE0 and BE1, for example, but not BE2 or BE3.

CHCHK

Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu.

CHRDY

Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end the bus cycle. Holding this line low for too long can cause problems on some systems. CHRDY and NOWS should not be used simultaneously. This may cause problems with some bus controllers.

CMD

Command Phase. This signal indicates that the current bus cycle is in the command phase. After the start phase (see START), the data is transferred during the CMD phase. CMD remains asserted from the falling edge of START until the end of the bus cycle.

SD0-SD16

System Data lines. They are bidrectional and tri-state.

DAKx

DMA Acknowledge.

DRQx

DMA Request.

EX16

EISA Slave Size 16. This is used by the slave device to inform the bus master that it is capable of 16 bit transfers.

EX32

EISA Slave Size 32. This is used by the slave device to inform the bus master that it is capable of 32 bit transfers.

EXRDY

EISA Ready. If this signal is asserted, the cycle will end on the next rising edge of BCLK. The slave device drives this signal low to insert wait states.

IO16

I/O size 16. Generated by a 16 bit slave when addressed by a bus master.

IORC

I/O Read Command line.

IOWC

I/O Write Command line.

IRQx

Interrupt Request. IRQ2 has the highest priority.

LAxx

Latchable Address lines.

LOCK

Asserting this signal prevents other bus masters from requesting control of the bus.

MAKx

Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been granted.

MASTER16

16 bit bus master. Generated by the ISA bus master when initiating a bus cycle.

M/IO

Memory/Input-Output. This is used to indicate whether the current bus cycle is a memory or an I/O operation.

M16

Memory Access, 16 bit

MRDC

Memory Read Command line.

MREQx

Master Request for Slot x: This is a slot specific request for the device to become the bus master.

MSBURST

Master Burst. The bus master asserts this signal in response to SLBURST. This tells the slave device that the bus master is also capable of burst cycles.

MWTC

Memory Write Command line.

NOWS

No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both signals should not be active simultaneously.

OSC

Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies.

REFRESH

Refresh. Generated when the refresh logic is bus master.

RESDRV

This signal goes low when the machine is powered up. Driving it low will force a system reset.

SA0-SA19

System Address Lines, tri-state.

SBHE

System Bus High Enable, tristate. Indicates a 16 bit data transfer.

SLBURST

Slave Burst. The slave device uses this to indicate that it is capable of burst cycles. The bus master will respond with MSBURST if it is also capable of burst cycles.

SMRDC

Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area.

SMWTC

Standard Memory Write Commmand line. Indicates a memory write in the lower 1 MB area.

START

Start Phase. This signal is low when the current bus cycle is in the start phase. Address and M/IO signals are decoded during this phase. Data is transferred during the command phase (indicated by CMD).

TC

Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete.

W/R

Write or Read. Used to indicate if the current bus cycle is a read or a write operation.

 
 

 
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