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+4 User Port

  • 26-11-2009, 13:31
  • Просмотров: 2095

+4 User Port

Available on Commodore +4 computer.

UNKNOWN (at the Computer)

UNKNOWN CONNECTOR at the Computer.

Pin Name Description
1 GND Ground
2 +5V +5 VDC
3 /BRESET ?
4 P2/CSE Data 2/Cassette Sense
5 P3 Data 3
6 P4 Data 4
7 P5 Data 5
8 RxC Receive Clock
9 ATN Attention?
10 +9V +9 VAC
11 +9V +9 VAC
12 GND Ground
A GND Ground
B P0 Data 0
C RxD Receive Data
D RTS Request to Send
E DTR Data Terminal Ready
F P7 Data 7
G DCD Data Carrier Detect
H P6 Data 6
I CTS Clear to Send
J DSR Data Set Ready
K TxD Transmit Data
L GND Ground
 
 

Video Expansion (Amiga)

36+54 PIN EDGE CONNECTOR (At the computer)

36+54 PIN EDGE CONNECTOR at the computer.

Pin Name Dir Description
1 RGB16 --> Red Bit 0
2 RGB17 --> Red Bit 1
3 LINELF --> Audio Line Out Left
4 LINERT --> Audio Line Out Right
5 C28D --> Pixel-Synchronous Clock
6 +5V - +5 Volts DC (1 A)
7 ARED --> Analog Red
8 +5V - +5 Volts DC (1 A)
9 GND - Digital Ground
10 +12V - +12 Volts DC (40 mA)
11 AGREEN --> Analog Green
12 GND - Digital Ground
13 GND - Digital Ground
14 /CSYNC --> Composite Sync
15 ABLUE --> Analog Blue
16 /XCLKEN <-- Genlock Clock Enable
17 GND - Digital Ground
18 BURST --> Burst Gate
19 /C4 --> 3.55/3.58 MHz Clock
20 GND - Digital Ground
21 GND - Digital Ground
22 /HSYNC --> Horizontal Sync (47 Ohm)
23 RGB4 --> Blue Bit 4
24 GND - Digital Ground
25 RGB7 --> Blue Bit 7
26 /VSYNC --> Vertical Sync (47 Ohm)
27 RGB15 --> Green Bit 7
28 BLANK --> Video Blank
29 RGB23 --> Red 7
30 /PIXELSW --> Genlock Overlay (47 Ohm)
31 -5V - -5 Volts DC
32 GND - Digital Ground
33 /XCLK <-- Genlock Clock
34 /C1 --> C1 Clock
35 +5V - +5 Volts DC (1 A)
36 PSTROBE --> Printer Port Handshake
       
1 GND - Digital Ground
2 RGB20 --> Red Bit 4
3 RGB21 --> Red Bit 5
4 RGB22 --> Red Bit 6
5 GND - Digital Ground
6 RGB12 --> Green Bit 4
7 RGB13 --> Green Bit 5
8 RGB14 --> Green Bit 6
9 GND - Digital Ground
10 RGB5 --> Blue Bit 5
11 RGB6 --> Blue Bit 6
12 GND - Ground
13 SOG --> Sync-On-Green Indicator
14 TBASE --> 50/60 Hz Software Clock Timebase
15 CDAC --> 7.09/7.16 MHz Clock
16 PPOUT <-> Printer Port Paper Out
17 /C3 --> 3.55/3.58 MHz Clock
18 PBUSY <-> Printer Port Busy
19 /LPEN <-- Light Pen Input
20 /PACK <-> Printer Port Acknowledge Handshake
21 PSEL --> Printer Port Select
22 GND - Digital Ground
23 PPD0 <-> Printer Port Data Bit 0
24 PPD1 <-> Printer Port Data Bit 1
25 PPD2 <-> Printer Port Data Bit 2
26 PPD3 <-> Printer Port Data Bit 3
27 PPD4 <-> Printer Port Data Bit 4
28 PPD5 <-> Printer Port Data Bit 5
29 PPD6 <-> Printer Port Data Bit 6
30 PPD7 <-> Printer Port Data Bit 7
31 /LED --> LED (Audio filter bypass) Setting
32 GND - Digital Ground
33 RAWLF --> Raw (Unfiltered) Audio Left
34 AGND - Audio Ground
35 RAWRT --> Raw (Unfiltered) Audio Right
36 AGND - Audio Ground
37 n/c - Reserved for future expansion
38 n/c - Reserved for future expansion
39 GND - Digital Ground
40 GND - Digital Ground
41 n/c - Reserved for future expansion
42 n/c - Reserved for future expansion
43 GND - Digital Ground
44 GND - Digital Ground
45 RGB18 --> Red Bit 2
46 RGB19 --> Red Bit 3
47 RGB8 --> Green Bit 0
48 RGB9 --> Green Bit 1
49 RGB10 --> Green Bit 2
50 RGB11 --> Green Bit 3
51 RGB0 --> Blue Bit 0
52 RGB1 --> Blue Bit 1
53 RGB2 --> Blue Bit 2
54 RGB3 --> Blue Bit 3
Note: Direction is Motherboard relative Card.
Note: Do not mix analog & digital grounds.
 
 

Amiga 1000 Ramex

60 PIN EDGE CONNECTOR (.156) (At the computer)

60 PIN EDGE CONNECTOR (.156") at the computer.

PinNameDescription
1 GND Ground
2 D15 Data 15
3 +5V +5 Volts DC
4 D12 Data 12
5 GND Ground
6 D11 Data 11
7 +5V +5 Volts DC
8 D8 Data 8
9 GND Ground
10 D7 Data 7
11 +5V +5 Volts DC
12 D4 Data 4
13 GND Ground
14 D3 Data 3
15 +5V +5 Volts DC
16 D0 Data 0
17 GND Ground
18 DRA4
19 DRA5
20 DRA6
21 DRA7
22 GND Ground
23 /RAS
24 GND Ground
25 GND Ground
26 /CASU0
27 GND Ground
28 /CASL0
29 +5V +5 Volts DC
30 +5V +5 Volts DC
A GND Ground
B D14 Data 14
C +5V +5 Volts DC
D D13 Data 13
E GND Ground
F D10 Data 10
H +5V +5 Volts DC
J D9 Data 9
K GND Ground
L D6 Data 6
M +5V +5 Volts DC
N D5 Data 5
P GND Ground
R D2 Data 2
S +5V +5 Volts DC
T D1 Data 1
U GND Ground
V DRA3
W DRA2
X DRA1
Y DRA0
Z GND Ground
AA /RRW
BB GND Ground
CC GND Ground
DD /CASU1
EE GND Ground
FF /CASL1
HH +5V +5 Volts DC
JJ +5V +5 Volts DC
 

Amiga 1200 CPU-port

UNKNOWN (At the computer)

UNKNOWN CONNECTOR at the computer.

PinNameDescription
1 n/c Reserved
2 n/c Reserved
3 n/c Reserved
4 n/c Reserved
5 n/c Reserved
6 n/c Reserved
7 n/c Reserved
8 n/c Reserved
9 GND Ground
10 +5V +5 Volts DC
11 A23 Address 23
12 A22 Address 22
13 A21 Address 21
14 A20 Address 20
15 A19 Address 19
16 A18 Address 18
17 A17 Address 17
18 A16 Address 16
19 GND Ground
20 +5V +5 Volts DC
21 A15 Address 15
22 A14 Address 14
23 A13 Address 13
24 A12 Address 12
25 A11 Address 11
26 A10 Address 10
27 A9 Address 9
28 A8 Address 8
29 GND Ground
30 +5V +5 Volts DC
31 A7 Address 7
32 A6 Address 6
33 A5 Address 5
34 A4 Address 4
35 A3 Address 3
36 A2 Address 2
37 A1 Address 1
38 A0 Address 0
39 GND Ground
40 +5V +5 Volts DC
41 D31 Data 31
42 D30 Data 30
43 D29 Data 29
44 D28 Data 28
45 D27 Data 27
46 D26 Data 26
47 D25 Data 25
48 D24 Data 24
49 GND Ground
50 +5V +5 Volts DC
51 D23 Data 23
52 D22 Data 22
53 D21 Data 21
54 D20 Data 20
55 D19 Data 19
56 D18 Data 18
57 D17 Data 17
58 D16 Data 16
59 GND Ground
60 +5V +5 Volts DC
61 D15 Data 15
62 D14 Data 14
63 D13 Data 13
64 D12 Data 12
65 D11 Data 11
66 D10 Data 10
67 D9 Data 9
68 D8 Data 8
69 GND Ground
70 +5V +5 Volts DC
71 D7 Data 7
72 D6 Data 6
73 D5 Data 5
74 D4 Data 4
75 D3 Data 3
76 D2 Data 2
77 D1 Data 1
78 D0 Data 0
79 GND Ground
80 +5V +5 Volts DC
81 /IPL2
82 /IPL1
83 /IPL0
84 n/c Reserved
85 /RST Reset
86 /HLT Halt
87 n/c Reserved
88 n/c Reserved
89 SIZE1
90 SIZE0
91 /AS Address Strobe
92 /DS Data Strobe
93 R/W Read/Write
94 /BERR Bus Error
95 n/c Reserved
96 /AVEC
97 /DSACK1
98 /DSACK2
99 CPUCKLA
100 ECLOCK EClock pulse
101 GND Ground
102 +5V +5 Volts DC
103 FC2 Processor Status 2
104 FC1 Processor Status 1
105 FC0 Processor Status 0
106 /RMC
107 n/c Reserved
108 n/c Reserved
109 n/c Reserved
110 n/c Reserved
111 /BR Slot specific Bus Arbitration
112 /BG Slot specific Bus Arbitration
113 n/c Reserved
114 /BOSS
115 /FPUCS FPU Chip select
116 /FPUSENSE FPU Sense
117 CCKA
118 /RESET Reset
119 GND Ground
120 +5V +5 Volts DC
121 /NETCS
122 /SPARECS
123 /RTCCS Realtime Clock Chip select
124 /FLASH
125 /REG
126 /CCENA
127 /WAIT
128 /KBRESET Keyboard reset
129 /IORD IO Read
130 /IOWR IO Write
131 /OE Output enable
132 /WE
133 /OVR /DTACK Override
134 XRDY External Ready
135 /ZORRO
136 /WIDE
137 /INT2 Interrupt level 2
138 /INT6 Interrupt level 6
139 GND Ground
140 +5V +5 Volts DC
141 SYSTEM1 System1 Ground
142 SYSTEM0 System0 Ground
143 /xRxD
144 /xTxD
145 /CONFIG OUT
146 AGND Audio Ground
147 ALEFT Audio Left
148 ARIGHT Audio Right
149 +12V +12 Volts DC
150 -12V -12 Volts DC
 

Zorro II/III

100 PIN EDGE CONNECTOR (At the computer)

100 PIN EDGE CONNECTOR at the computer.

PinPhysical
Name
Zorro II
Name
Zorro III
Address Phase
Zorro III
Data Phase
1 Ground Ground Ground Ground
2 Ground Ground Ground Ground
3 Ground Ground Ground Ground
4 Ground Ground Ground Ground
5 +5VDC +5VDC +5VDC +5VDC
6 +5VDC +5VDC +5VDC +5VDC
7 /OWN /OWN /OWN /OWN
8 -5VDC -5VDC -5VDC -5VDC
9 /SLAVEn /SLAVEn /SLAVEn /SLAVEn
10 +12VDC +12VDC +12VDC +12VDC
11 /CFGOUTn /CFGOUTn /CFGOUTn /CFGOUTn
12 /CFGINn /CFGINn /CFGINn /CFGINn
13 Ground Ground Ground Ground
14 /C3 /C3 Clock /C3 Clock /C3 Clock
15 CDAC CDAC Clock CDAC Clock CDAC Clock
16 /C1 /C1 Clock /C1 Clock /C1 Clock
17 /CINH /OVR /CINH /CINH
18 /MTCR XRDY /MTCR /MTCR
19 /INT2 /INT2 /INT2 /INT2
20 -12VDC -12VDC -12VDC -12VDC
21 A5 A5 A5 A5
22 /INT6 /INT6 /INT6 /INT6
23 A6 A6 A6 A6
24 A4 A4 A4 A4
25 Ground Ground Ground Ground
26 A3 A3 A3 A3
27 A2 A2 A2 A2
28 A7 A7 A7 A7
29 /LOCK A1 /LOCK /LOCK
30 AD8 A8 A8 D0
31 FC0 FC0 FC0 FC0
32 AD9 A9 A9 D1
33 FC1 FC1 FC1 FC1
34 AD10 A10 A10 D2
35 FC2 FC2 FC2 FC2
36 AD11 A11 A11 D3
37 Ground Ground Ground Ground
38 AD12 A12 A12 D4
39 AD13 A13 A13 D5
40 Reserved (/EINT7) Reserved Reserved
41 AD14 A14 A14 D6
42 Reserved (/EINT5) Reserved Reserved
43 AD15 A15 A15 D7
44 Reserved (/EINT4) Reserved Reserved
45 AD16 A16 A16 D8
46 /BERR /BERR /BERR /BERR
47 AD17 A17 A17 D9
48 /MTACK (/VPA) /MTACK /MTACK
49 Ground Ground Ground Ground
50 E Clock E Clock E Clock E Clock
51 /DS0 (/VMA) /DS0 /DS0
52 AD18 A18 A18 D10
53 /RESET /RST /RESET /RESET
54 AD19 A19 A19 D11
55 /HLT /HLT /HLT /HLT
56 AD20 A20 A20 D12
57 AD22 A22 A22 D14
58 AD21 A21 A21 D13
59 AD23 A23 A23 D15
60 /BRn /BRn /BRn /BRn
61 Ground Ground Ground Ground
62 /BGACK /BGACK /BGACK /BGACK
63 AD31 D15 A31 D31
64 /BGn /BGn /BGn /BGn
65 AD30 D14 A30 D30
66 /DTACK /DTACK /DTACK /DTACK
67 AD29 D13 A29 D29
68 READ READ READ READ
69 AD28 D12 A28 D28
70 /DS2 /LDS /DS2 /DS2
71 AD27 D11 A27 D27
72 /DS3 /UDS /DS3 /DS3
73 Ground Ground Ground Ground
74 /CCS /AS /CCS /CCS
75 SD0 D0 Reserved D16
76 AD26 D10 A26 D26
77 SD1 D1 Reserved D17
78 AD25 D9 A25 D25
79 SD2 D2 Reserved D18
80 AD24 D8 A24 D24
81 SD3 D3 Reserved D19
82 SD7 D7 Reserved D23
83 SD4 D4 Reserved D20
84 SD6 D6 Reserved D22
85 Ground Ground Ground Ground
86 SD5 D5 Reserved D21
87 Ground Ground Ground Ground
88 Ground Ground Ground Ground
89 Ground Ground Ground Ground
90 Ground Ground Ground Ground
91 SenseZ3 Ground SenseZ3 SenseZ3
92 7M E7M 7M 7M
93 DOE DOE DOE DOE
94 /IORST /BUSRST /IORST /IORST
95 /BCLR /GBG /BCLR /BCLR
96 Reserved (/EINT1) Reserved Reserved
97 /FCS No Connect /FCS /FCS
98 /DS1 No Connect /DS1 /DS1
99 Ground Ground Ground Ground
100 Ground Ground Ground Ground
 

NuBus 90

Availble on old Apple Macintosh computers.

UNKNOWN CONNECTOR (At the card)
UNKNOWN CONNECTOR (At the computer)

UNKNOWN CONNECTOR at the card.
UNKNOWN CONNECTOR at the computer.

Row A

PinNameDescription
1 -12 V -12 VDC
2 SB0
3 /SPV
4 /SP
5 /TM1
6 /AD1 Address/Data 1
7 /AD3 Address/Data 3
8 /AD5 Address/Data 5
9 /AD7 Address/Data 7
10 /AD9 Address/Data 9
11 /AD11 Address/Data 11
12 /AD13 Address/Data 13
13 /AD15 Address/Data 15
14 /AD17 Address/Data 17
15 /AD19 Address/Data 19
16 /AD21 Address/Data 21
17 /AD23 Address/Data 23
18 /AD25 Address/Data 25
19 /AD27 Address/Data 27
20 /AD29 Address/Data 29
21 /AD31 Address/Data 31
22 GND Ground
23 GND Ground
24 /ARB1
25 /ARB3
26 /ID1
27 /ID3
28 /ACK
29 +5 V +5 VDC
30 /RQST
31 /NMRQ
32 +12 V +12 VDC

Row B

PinNameDescription
1 -12 V -12 VDC
2 GND Ground
3 GND Ground
4 +5 V +5 VDC
5 +5 V +5 VDC
6 +5 V +5 VDC
7 +5 V +5 VDC
8 /TM2
9 /CM0
10 /CM1
11 /CM2
12 GND Ground
13 GND Ground
14 GND Ground
15 GND Ground
16 GND Ground
17 GND Ground
18 GND Ground
19 GND Ground
20 GND Ground
21 GND Ground
22 GND Ground
23 GND Ground
24 /CLK2X
25 STDBYPWR
26 /CLK2XEN
27 /CBUSY
28 +5 V +5 VDC
29 +5 V +5 VDC
30 GND Ground
31 GND Ground
32 +12 V +12 VDC

Row C

PinNameDescription
1 /RESET Reset
2 SB1
3 +5 V +5 VDC
4 +5 V +5 VDC
5 /TM0
6 /AD0 Address/Data 0
7 /AD2 Address/Data 2
8 /AD4 Address/Data 4
9 /AD6 Address/Data 6
10 /AD8 Address/Data 8
11 /AD10 Address/Data 10
12 /AD12 Address/Data 12
13 /AD14 Address/Data 14
14 /AD16 Address/Data 16
15 /AD18 Address/Data 18
16 /AD20 Address/Data 20
17 /AD22 Address/Data 22
18 /AD24 Address/Data 24
19 /AD26 Address/Data 26
20 /AD28 Address/Data 28
21 /AD30 Address/Data 30
22 GND Ground
23 /PFW
24 /ARB0
25 /ARB2
26 /ID0
27 /ID2
28 /START
29 +5 V +5 VDC
30 +5 V +5 VDC
31 GND Ground
32 /CLK Clock
 

NuBus

Availble on old Apple Macintosh computers.
Standard: IEEE 1196, "Nubus-A simple 32-bit backplane bus"

UNKNOWN CONNECTOR (At the card)
UNKNOWN CONNECTOR (At the computer)

UNKNOWN CONNECTOR at the card.
UNKNOWN CONNECTOR at the computer.

Row A

PinNameDescription
1 -12 V -12 VDC
2 -
3 /SPV
4 /SP
5 /TM1
6 /AD1 Address/Data 1
7 /AD3 Address/Data 3
8 /AD5 Address/Data 5
9 /AD7 Address/Data 7
10 /AD9 Address/Data 9
11 /AD11 Address/Data 11
12 /AD13 Address/Data 13
13 /AD15 Address/Data 15
14 /AD17 Address/Data 17
15 /AD19 Address/Data 19
16 /AD21 Address/Data 21
17 /AD23 Address/Data 23
18 /AD25 Address/Data 25
19 /AD27 Address/Data 27
20 /AD29 Address/Data 29
21 /AD31 Address/Data 31
22 GND Ground
23 GND Ground
24 /ARB1
25 /ARB3
26 /ID1
27 /ID3
28 /ACK
29 +5 V +5 VDC
30 /RQST
31 /NMRQ
32 +12 V +12 VDC

Row B

PinNameDescription
1 -12 V -12 VDC
2 GND Ground
3 GND Ground
4 +5 V +5 VDC
5 +5 V +5 VDC
6 +5 V +5 VDC
7 +5 V +5 VDC
8 * Reserved ?
9 * Reserved ?
10 * Reserved ?
11 * Reserved ?
12 GND Ground
13 GND Ground
14 GND Ground
15 GND Ground
16 GND Ground
17 GND Ground
18 GND Ground
19 GND Ground
20 GND Ground
21 GND Ground
22 GND Ground
23 GND Ground
24 ** Reserved ?
25 ** Reserved ?
26 ** Reserved ?
27 ** Reserved ?
28 +5 V +5 VDC
29 +5 V +5 VDC
30 GND Ground
31 GND Ground
32 +12 V

Row C

PinNameDescription
1 /RESET Reset
2 -
3 +5 V +5 VDC
4 +5 V +5 VDC
5 /TM0
6 /AD0 Address/Data 0
7 /AD2 Address/Data 2
8 /AD4 Address/Data 4
9 /AD6 Address/Data 6
10 /AD8 Address/Data 8
11 /AD10 Address/Data 10
12 /AD12 Address/Data 12
13 /AD14 Address/Data 14
14 /AD16 Address/Data 16
15 /AD18 Address/Data 18
16 /AD20 Address/Data 20
17 /AD22 Address/Data 22
18 /AD24 Address/Data 24
19 /AD26 Address/Data 26
20 /AD28 Address/Data 28
21 /AD30 Address/Data 30
22 GND Ground
23 /PFW
24 /ARB0
25 /ARB2
26 /ID0
27 /ID2
28 /START
29 +5 V +5 VDC
30 +5 V +5 VDC
31 GND Ground
32 /CLK Clock
 

VESA LocalBus (VLB)

VLB=VESA Local Bus.
VESA=Video Electronics Standards Association.

58 PIN EDGE CONNECTOR MALE (At the card)
58 PIN EDGE CONNECTOR FEMALE (At the computer)

58 PIN EDGE CONNECTOR MALE at the card.
58 PIN EDGE CONNECTOR FEMALE at the computer.

PinNameDescription
A1 D1 Data 1
A2 D3 Data 3
A3 GND Ground
A4 D5 Data 5
A5 D7 Data 7
A6 D9 Data 9
A7 D11 Data 11
A8 D13 Data 13
A9 D15 Data 15
A10 GND Ground
A11 D17 Data 17
A12 Vcc +5 VDC
A13 D19 Data 19
A14 D21 Data 21
A15 D23 Data 23
A16 D25 Data 25
A17 GND Ground
A18 D27 Data 27
A19 D29 Data 2
A20 D31 Data 31
A21 A30 Address 30
A22 A28 Address 28
A23 A26 Address 26
A24 GND Ground
A25 A24 Address 24
A26 A22 Address 22
A27 VCC +5 VDC
A28 A20 Address 20
A29 A18 Address 18
A30 A16 Address 16
A31 A14 Address 14
A32 A12 Address 12
A33 A10 Address 10
A34 A8 Address 8
A35 GND Ground
A36 A6 Address 6
A37 A4 Address 4
A38 WBACK# Write Back
A39 BE0# Byte Enable 0
A40 VCC +5 VDC
A41 BE1# Byte Enable 1
A42 BE2# Byte Enable 2
A43 GND Ground
A44 BE3# Byte Enable 3
A45 ADS# Address Strobe
A48 LRDY# Local Ready
A49 LDEV Local Device
A50 LREQ Local Request
A51 GND Ground
A52 LGNT Local Grant
A53 VCC +5 VDC
A54 ID2 Identification 2
A55 ID3 Identification 3
A56 ID4 Identification 4
A57 LKEN#
A58 LEADS# Local Enable Address Strobe
B1 D0 Data 0
B2 D2 Data 2
B3 D4 Data 4
B4 D6 Data 6
B5 D8 Data 8
B6 GND Ground
B7 D10 Data 10
B8 D12 Data 12
B9 VCC +5 VDC
B10 D14 Data 14
B11 D16 Data 16
B12 D18 Data 18
B13 D20 Data 20
B14 GND Ground
B15 D22 Data 22
B16 D24 Data 24
B17 D26 Data 26
B18 D28 Data 28
B19 D30 Data 30
B20 VCC +5 VDC
B21 A31 Address 31
B22 GND Ground
B23 A29 Address 29
B24 A27 Address 27
B25 A25 Address 25
B26 A23 Address 23
B27 A21 Address 21
B28 A19 Address 19
B29 GND Ground
B30 A17 Address 17
B31 A15 Address 15
B32 VCC +5 VDC
B33 A13 Address 13
B34 A11 Address 11
B35 A9 Address 9
B36 A7 Address 7
B37 A5 Address 5
B38 GND Ground
B39 A3 Address 3
B40 A2 Address 2
B41 n/c Not connected
B42 RESET# Reset
B43 DC# Data/Command
B44 M/IO# Memory/IO
B45 W/R# Write/Read
B48 RDYRTN# Ready Return
B49 GND Ground
B50 IRQ9 Interrupt 9
B51 BRDY# Burst Ready
B52 BLAST# Burst Last
B53 ID0 Identification 0
B54 ID1 Identification 1
B55 GND Ground
B56 LCLK Local Clock
B57 VCC +5 VDC
B58 LBS16# Local Bus Size 16
 
 

EISA

EISA=Extended Industry Standard Architecture.
Developed by Compaq, AST, Zenith, Tandy...

+---------------------------------------------+
|            (component side)                 |
|                                             |
|___________ ISA-16bit __       ISA-8bit    __|
            |||||||||||  |||||||||||||||||||  A1(front)/B1(back)
             | | | | |    | | | | | | | | |  EISA: E1(front)/F1(back)
                   C1/D1
                  G1/H1
A,C,E,G=Component Side
A,B,F,H=Sold Side

NOT DRAWN YET (At the computer)

62+38 PIN EDGE CONNECTOR at the computer.

Pin Name Description
E1 CMD# Command Phase
E2 START# Start Phase
E3 EXRDY EISA Ready
E4 EX32# EISA Slave Size 32
E5 GND Ground
E6 KEY Access Key
E7 EX16# EISA Slave Size 16
E8 SLBURST# Slave Burst
E9 MSBURST# Master Burst
E10 W/R# Write/Read
E11 GND Ground
E12 RES Reserved
E13 RES Reserved
E14 RES Reserved
E15 GND Ground
E16 KEY Access Key
E17 BE1# Byte Enable 1
E18 LA31# Latchable Addressline 31
E19 GND Ground
E20 LA30# Latchable Addressline 30
E21 LA28# Latchable Addressline 28
E22 LA27# Latchable Addressline 27
E23 LA25# Latchable Addressline 25
E24 GND Ground
E25 KEY Access Key
E26 LA15 Latchable Addressline 15
E27 LA13 Latchable Addressline 13
E28 LA12 Latchable Addressline 12
E29 LA11 Latchable Addressline 11
E30 GND Ground
E31 LA9 Latchable Addressline 9
     
F1 GND Ground
F2 +5V +5 VDC
F3 +5V +5 VDC
F4 ---  
F5 ---  
F6 KEY Access Key
F7 ---  
F8 ---  
F9 +12V +12 VDC
F10 M/IO# Memory/Input-Output
F11 LOCK# Lock bus
F12 RES Reserved
F13 GND Ground
F14 RES Reserved
F15 BE3# Byte Enable 3
F16 KEY Access Key
F17 BE2# Byte Enable 2
F18 BE0# Byte Enable 0
F19 GND Ground
F20 +5V +5 VDC
F21 LA29# Latchable Addressline 29
F22 GND Ground
F23 LA26# Latchable Addressline 26
F24 LA24# Latchable Addressline 24
F25 KEY Access Key
F26 LA16 Latchable Addressline 16
F27 LA14 Latchable Addressline 14
F28 +5V +5 VDC
F29 +5V +5 VDC
F30 GND Ground
F31 LA10 Latchable Addressline 10
     
G1 LA7 Latchable Addressline 7
G2 GND Ground
G3 LA4 Latchable Addressline 4
G4 LA3 Latchable Addressline 3
G5 GND Ground
G6 KEY Access Key
G7 D17 Data 17
G8 D19 Data 19
G9 D20 Data 20
G10 D22 Data 22
G11 GND Ground
G12 D25 Data 25
G13 D26 Data 26
G14 D28 Data 28
G15 KEY Access Key
G16 GND Ground
G17 D30 Data 30
G18 D31 Data 31
G19 MREQx Master Request
     
H1 LA8 Latchable Addressline 8
H2 LA6 Latchable Addressline 6
H3 LA5 Latchable Addressline 5
H4 +5V +5 VDC
H5 LA2 Latchable Addressline 2
H6 KEY Access Key
H7 D16 Data 16
H8 D18 Data 18
H9 GND Ground
H10 D21 Data 21
H11 D23 Data 23
H12 D24 Data 24
H13 GND Ground
H14 D27 Data 27
H15 KEY Access Key
H16 D29 Data 29
H17 +5V +5 VDC
H18 +5V +5 VDC
H19 MAKx Master Acknowledge
 
 
0

ISA

  • 23-02-2009, 23:52
  • Просмотров: 3014
 

ISA

ISA=Industry Standard Architecture

62+36 PIN EDGE CONNECTOR MALE (At the card)
62+36 PIN EDGE CONNECTOR FEMALE (At the computer)

62+36 PIN EDGE CONNECTOR MALE at the card.
62+36 PIN EDGE CONNECTOR FEMALE at the computer.

Pin Name Dir Description
A1 /I/O CH CK <-- I/O channel check; active low=parity error
A2 D7 <-> Data bit 7
A3 D6 <-> Data bit 6
A4 D5 <-> Data bit 5
A5 D4 <-> Data bit 4
A6 D3 <-> Data bit 3
A7 D2 <-> Data bit 2
A8 D1 <-> Data bit 1
A9 D0 <-> Data bit 0
A10 I/O CH RDY <-- I/O Channel ready, pulled low to lengthen memory cycles
A11 AEN --> Address enable; active high when DMA controls bus
A12 A19 --> Address bit 19
A13 A18 --> Address bit 18
A14 A17 --> Address bit 17
A15 A16 --> Address bit 16
A16 A15 --> Address bit 15
A17 A14 --> Address bit 14
A18 A13 --> Address bit 13
A19 A12 --> Address bit 12
A20 A11 --> Address bit 11
A21 A10 --> Address bit 10
A22 A9 --> Address bit 9
A23 A8 --> Address bit 8
A24 A7 --> Address bit 7
A25 A6 --> Address bit 6
A26 A5 --> Address bit 5
A27 A4 --> Address bit 4
A28 A3 --> Address bit 3
A29 A2 --> Address bit 2
A30 A1 --> Address bit 1
A31 A0 --> Address bit 0
B1 GND Ground
B2 RESET --> Active high to reset or initialize system logic
B3 +5V +5 VDC
B4 IRQ2 <-- Interrupt Request 2
B5 -5VDC -5 VDC
B6 DRQ2 <-- DMA Request 2
B7 -12VDC -12 VDC
B8 /NOWS <-- No WaitState
B9 +12VDC +12 VDC
B10 GND Ground
B11 /SMEMW --> System Memory Write
B12 /SMEMR --> System Memory Read
B13 /IOW --> I/O Write
B14 /IOR --> I/O Read
B15 /DACK3 --> DMA Acknowledge 3
B16 DRQ3 <-- DMA Request 3
B17 /DACK1 --> DMA Acknowledge 1
B18 DRQ1 <-- DMA Request 1
B19 /REFRESH <-> Refresh
B20 CLOCK --> System Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
B21 IRQ7 <-- Interrupt Request 7
B22 IRQ6 <-- Interrupt Request 6
B23 IRQ5 <-- Interrupt Request 5
B24 IRQ4 <-- Interrupt Request 4
B25 IRQ3 <-- Interrupt Request 3
B26 /DACK2 --> DMA Acknowledge 2
B27 T/C --> Terminal count; pulses high when DMA term. count reached
B28 ALE --> Address Latch Enable
B29 +5V +5 VDC
B30 OSC --> High-speed Clock (70 ns, 1431818 MHz, 50% duty cycle)
B31 GND Ground
C1 SBHE <-> System bus high enable (data availble on SD8-15)
C2 LA23 <-> Address bit 23
C3 LA22 <-> Address bit 22
C4 LA21 <-> Address bit 21
C5 LA20 <-> Address bit 20
C6 LA18 <-> Address bit 19
C7 LA17 <-> Address bit 18
C8 LA16 <-> Address bit 17
C9 /MEMR <-> Memory Read (Active on all memory read cycles)
C10 /MEMW <-> Memory Write (Active on all memory write cycles)
C11 SD08 <-> Data bit 8
C12 SD09 <-> Data bit 9
C13 SD10 <-> Data bit 10
C14 SD11 <-> Data bit 11
C15 SD12 <-> Data bit 12
C16 SD13 <-> Data bit 13
C17 SD14 <-> Data bit 14
C18 SD15 <-> Data bit 15
D1 /MEMCS16 <-- Memory 16-bit chip select (1 wait, 16-bit memory cycle)
D2 /IOCS16 <-- I/O 16-bit chip select (1 wait, 16-bit I/O cycle)
D3 IRQ10 <-- Interrupt Request 10
D4 IRQ11 <-- Interrupt Request 11
D5 IRQ12 <-- Interrupt Request 12
D6 IRQ15 <-- Interrupt Request 15
D7 IRQ14 <-- Interrupt Request 14
D8 /DACK0 --> DMA Acknowledge 0
D9 DRQ0 <-- DMA Request 0
D10 /DACK5 --> DMA Acknowledge 5
D11 DRQ5 <-- DMA Request 5
D12 /DACK6 --> DMA Acknowledge 6
D13 DRQ6 <-- DMA Request 6
D14 /DACK7 --> DMA Acknowledge 7
D15 DRQ7 <-- DMA Request 7
D16 +5 V
D17 /MASTER <-- Used with DRQ to gain control of system
D18 GND Ground
Note: Direction is Motherboard relative ISA-Cards.
Note: B8 was /CARD SLCDTD on the XT. Card selected, activated by cards in XT's slot J8
 
 
 
 
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