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PC Card

16-bit bus defined by PCMCIA.

68 PIN ??? MALE (At the controller)
68 PIN ??? FEMALE (At the peripherals)

68 PIN ??? MALE at the controller.
68 PIN ??? FEMALE at the peripherals.

PinMemoryI/O+MemDescription
1 GND GND Ground
2 D3 D3 Data 3
3 D4 D4 Data 4
4 D5 D5 Data 5
5 D6 D6 Data 6
6 D7 D7 Data 7
7 CE1# CE1#
8 A10 A10 Address 10
9 OE# OE# Output Enable
10 A11 A11 Address 11
11 A9 A9 Address 9
12 A8 A8 Address 8
13 A13 A13 Address 13
14 A14 A14 Address 14
15 WE# WE# Write Enable ???
16 READY IREQ#
17 Vcc Vcc Vcc
18 Vpp1 Vpp1 Vpp1
19 A16 A16 Address 16
20 A15 A15 Address 15
21 A12 A12 Address 12
22 A7 A7 Address 7
23 A6 A6 Address 6
24 A5 A5 Address 5
25 A4 A4 Address 4
26 A3 A3 Address 3
27 A2 A2 Address 2
28 A1 A1 Address 1
29 A0 A0 Address 0
30 D0 D0 Data 0
31 D1 D1 Data 1
32 D2 D2 Data 2
33 WP IOIS16#
34 GND GND Ground
35 GND GND Ground
36 CD1# CD1# Card Detect 1
37 D11 D11 Data 11
38 D12 D12 Data 12
39 D13 D13 Data 13
40 D14 D14 Data 14
41 D15 D15 Data 15
42 CE2# CE2#
43 VS1# VS1#
44 RSRVD IORD# Reserved / IORD#
45 RSRVD IOWR# Reserved / IOWR#
46 A17 A17 Address 17
47 A18 A18 Address 18
48 A19 A19 Address 19
49 A20 A20 Address 20
50 A21 A21 Address 21
51 Vcc Vcc Vcc
52 Vpp2 Vpp2 Vpp2
53 A22 A22 Address 22
54 A23 A23 Address 23
55 A24 A24 Address 24
56 A25 A25 Address 25
57 VS2# VS2#
58 RESET RESET Reset
59 WAIT# WAIT#
60 RSRVD INPACK# Reserved / ???
61 REG# REG#
62 BVD2 SPKR# Battery Voltage 2 / Speaker ???
63 BVD1 STSCHG# Battery Voltage 1 / ???
64 D8 D8 Data 8
65 D9 D9 Data 9
66 D10 D10 Data 10
67 CD2# CD2#
68 GND GND Ground
 

CardBus

32-bit bus defined by PCMCIA.

68 PIN ??? MALE (At the controller)
68 PIN ??? FEMALE (At the peripherals)

68 PIN ??? MALE at the controller.
68 PIN ??? FEMALE at the peripherals.

PinNameDescription
1 GND Ground
2 CAD0 Address/Data 0
3 CAD1 Address/Data 1
4 CAD3 Address/Data 3
5 CAD5 Address/Data 5
6 CAD7 Address/Data 7
7 CCBE0# Command/Byte Enable 0
8 CAD9 Address/Data 9
9 CAD11 Address/Data 11
10 CAD12 Address/Data 12
11 CAD14 Address/Data 14
12 CCBE1# Command/Byte Enable 1
13 CPAR Parity
14 CPERR# Parity error
15 CGNT# Grant
16 CINT# Interrupt
17 Vcc Vcc
18 Vpp1 Vpp1
19 CCLK CCLK
20 CIRDY# Initiator Ready
21 CCBE2# Command/Byte Enable 2
22 CAD18 Address/Data 18
23 CAD20 Address/Data 20
24 CAD21 Address/Data 21
25 CAD22 Address/Data 22
26 CAD23 Address/Data 23
27 CAD24 Address/Data 24
28 CAD25 Address/Data 25
29 CAD26 Address/Data 26
30 CAD27 Address/Data 27
31 CAD29 Address/Data 29
32 RSRVD Reserved
33 CCLKRUN# CCLKRUN#
34 GND Ground
35 GND Ground
36 CCD1# Card Detect 1
37 CAD2 Address/Data 2
38 CAD4 Address/Data 4
39 CAD6 Address/Data 6
40 RSRVD Reserved
41 CAD8 Address/Data 8
42 CAD10 Address/Data 10
43 CVS1
44 CAD13 Address/Data 13
45 CAD15 Address/Data 15
46 CAD16 Address/Data 16
47 RSRVD Reserved
48 CBLOCK# Block ???
49 CSTOP# Stop transfer cycle
50 CDEVSEL# Device Select
51 Vcc Vcc
52 Vpp2 Vpp2
53 CTRDY# Target Ready
54 CFRAME# Address or Data phase
55 CAD17 Address/Data 17
56 CAD19 CAD19
57 CVS2
58 CRST# Reset
59 CSERR# System Error
60 CREQ# Request ???
61 CCBE3# Command/Byte Enable 3
62 CAUDIO Audio ???
63 CSTSCHG
64 CAD28 Address/Data 28
65 CAD30 Address/Data 30
66 CAD31 Address/Data 31
67 CCD2# Card Detect 2
68 GND Ground
 

Amiga 1200 CPU-port

UNKNOWN (At the computer)

UNKNOWN CONNECTOR at the computer.

PinNameDescription
1 n/c Reserved
2 n/c Reserved
3 n/c Reserved
4 n/c Reserved
5 n/c Reserved
6 n/c Reserved
7 n/c Reserved
8 n/c Reserved
9 GND Ground
10 +5V +5 Volts DC
11 A23 Address 23
12 A22 Address 22
13 A21 Address 21
14 A20 Address 20
15 A19 Address 19
16 A18 Address 18
17 A17 Address 17
18 A16 Address 16
19 GND Ground
20 +5V +5 Volts DC
21 A15 Address 15
22 A14 Address 14
23 A13 Address 13
24 A12 Address 12
25 A11 Address 11
26 A10 Address 10
27 A9 Address 9
28 A8 Address 8
29 GND Ground
30 +5V +5 Volts DC
31 A7 Address 7
32 A6 Address 6
33 A5 Address 5
34 A4 Address 4
35 A3 Address 3
36 A2 Address 2
37 A1 Address 1
38 A0 Address 0
39 GND Ground
40 +5V +5 Volts DC
41 D31 Data 31
42 D30 Data 30
43 D29 Data 29
44 D28 Data 28
45 D27 Data 27
46 D26 Data 26
47 D25 Data 25
48 D24 Data 24
49 GND Ground
50 +5V +5 Volts DC
51 D23 Data 23
52 D22 Data 22
53 D21 Data 21
54 D20 Data 20
55 D19 Data 19
56 D18 Data 18
57 D17 Data 17
58 D16 Data 16
59 GND Ground
60 +5V +5 Volts DC
61 D15 Data 15
62 D14 Data 14
63 D13 Data 13
64 D12 Data 12
65 D11 Data 11
66 D10 Data 10
67 D9 Data 9
68 D8 Data 8
69 GND Ground
70 +5V +5 Volts DC
71 D7 Data 7
72 D6 Data 6
73 D5 Data 5
74 D4 Data 4
75 D3 Data 3
76 D2 Data 2
77 D1 Data 1
78 D0 Data 0
79 GND Ground
80 +5V +5 Volts DC
81 /IPL2
82 /IPL1
83 /IPL0
84 n/c Reserved
85 /RST Reset
86 /HLT Halt
87 n/c Reserved
88 n/c Reserved
89 SIZE1
90 SIZE0
91 /AS Address Strobe
92 /DS Data Strobe
93 R/W Read/Write
94 /BERR Bus Error
95 n/c Reserved
96 /AVEC
97 /DSACK1
98 /DSACK2
99 CPUCKLA
100 ECLOCK EClock pulse
101 GND Ground
102 +5V +5 Volts DC
103 FC2 Processor Status 2
104 FC1 Processor Status 1
105 FC0 Processor Status 0
106 /RMC
107 n/c Reserved
108 n/c Reserved
109 n/c Reserved
110 n/c Reserved
111 /BR Slot specific Bus Arbitration
112 /BG Slot specific Bus Arbitration
113 n/c Reserved
114 /BOSS
115 /FPUCS FPU Chip select
116 /FPUSENSE FPU Sense
117 CCKA
118 /RESET Reset
119 GND Ground
120 +5V +5 Volts DC
121 /NETCS
122 /SPARECS
123 /RTCCS Realtime Clock Chip select
124 /FLASH
125 /REG
126 /CCENA
127 /WAIT
128 /KBRESET Keyboard reset
129 /IORD IO Read
130 /IOWR IO Write
131 /OE Output enable
132 /WE
133 /OVR /DTACK Override
134 XRDY External Ready
135 /ZORRO
136 /WIDE
137 /INT2 Interrupt level 2
138 /INT6 Interrupt level 6
139 GND Ground
140 +5V +5 Volts DC
141 SYSTEM1 System1 Ground
142 SYSTEM0 System0 Ground
143 /xRxD
144 /xTxD
145 /CONFIG OUT
146 AGND Audio Ground
147 ALEFT Audio Left
148 ARIGHT Audio Right
149 +12V +12 Volts DC
150 -12V -12 Volts DC
 

IndustrialPCI (IPCI)

PCI=Peripheral Component Interconnect.
IndustrialPCI is a a version of PCI adapted for industrial and/or embedded applications.

The IPCI connector has three parts:

  • Optional 60 pin PCI 64 bit extension (Top)
  • Mandatory 120 pin PCI 32 bit (Middle)
  • Optional 60 pin Custom I/O (Bottom)

UNKNOWN (At the backplane)
UNKNOWN (At the device (card))

UNKNOWN CONNECTOR at the backplane.
UNKNOWN CONNECTOR at the device (card).

System Slot (Middle)

PinNameDescriptionNote
A1 +3,3V +3.3 VDC
A2 AD2 Address 2
A3 AD6 Address 6
A4 GND Ground
A5 AD10 Address 10
A6 AD13 Address 13
A7 GND Ground
A8 SDONE Snoop Done 1
A9 GND Ground
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18
A12 GND Ground
A13 +5V +5 VDC
A14 AD24 Address 24
A15 AD27 Address 27
A16 GND Ground
A17 REQ2 Request 2 1
A18 GND Ground
A19 CLK1 33 or 66 MHz Clock
A20 CLK2
A21 GND Ground
A22 CLK3
A23 CLK4
A24 +3,3V +3.3 VDC
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3
B3 +5V +5 VDC
B4 AD8 Address 8
B5 +3,3V +3.3 VDC
B6 AD14 Address 14
B7 PAR Parity
B8 +3,3V +3.3 VDC
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2
B11 V(I/O) +3.3 or +5 VDC
B12 AD21 Address 21
B13 +3,3V +3.3 VDC
B14 V(I/O) +3.3 or +5 VDC
B15 AD28 Address 28
B16 AD31 Address 31
B17 +3,3V +3.3 VDC
B18 GNT3 Grant 3
B19 RST# Reset
B20 NMI# Non Maskable Interrupt
B21 X6 Reserved (6)
B22 +5V +5 VDC :
B23 RSTIN# 2
B24 USB+ Universal Serial Bus (USB)(+)
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground
C3 AD7 Address 7
C4 AD9 Address 9
C5 AD11 Address 11
C6 GND Ground
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground
C11 AD19 Address 19
C12 AD22 Address 22
C13 GND Ground
C14 AD25 Address 25
C15 GND Ground
C16 X1 Reserved (1)
C17 GNT2 Grant 2
C18 REQ4 Request 4 1
C19 SLEEP#/SDAT Sleep/Serial Data (I2C) 3
C20 X4 Reserved (4)
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC
C24 USB- Universal Serial Bus (USB)(-)
D1 AD0 Address 0
D2 AD4 Address 4
D3 C/BE0# Command, Byte Enable 0
D4 +3,3V +3.3 VDC
D5 AD12 Address 12
D6 AD15 Address 15
D7 V(I/O) +3.3 or +5 VDC
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16
D11 AD20 Address 20
D12 +5V +5 VDC
D13 +5V +5 VDC
D14 AD26 Address 26
D15 AD29 Address 29
D16 REQ1 Request 1 1
D17 REQ3 Request 3 1
D18 V(I/O) +3.3 or +5 VDC
D19 X2 Reserved (2)
D20 X5 Reserved (5)
D21 +3,3V +3.3 VDC
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)
E1 AD1 Address 1
E2 AD5 Address 5
E3 GND Ground
E4 M66EN Enable 66Mhz PCI-bus
E5 GND Ground
E6 C/BE1# Command, Byte Enable 1
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC
E9 IRDY# Initatior Ready 1
E10 AD17 Address 17
E11 GND Ground
E12 AD23 Address 23
E13 C/BE3# Command, Byte Enable 3
E14 GND Ground
E15 AD30 Address 30
E16 GNT1 Grant 1
E17 +5V +5 VDC
E18 GNT4 Grant 4
E19 X3 Reserved (3)
E20 GND Ground
E21 INTC# Interrupt C 1
E22 -12V -12 VDC
E23 +12V +12 VDC
E24 VBATT

1 = Pullup resistor of 2,7 kW on the System Slot (CPU).
2 = Pullup resistor of 330 W on the System Slot (CPU).
3 = Pullup resistor of 4,7 kW, if not supported by the System Slot (CPU).

Module Bus Slot (Middle)

PinNameDescriptionNote
A1 +3,3V +3.3 VDC
A2 AD2 Address 2
A3 AD6 Address 6
A4 GND Ground
A5 AD10 Address 10
A6 AD13 Address 13
A7 GND Ground
A8 SDONE Snoop Done 1
A9 GND Ground
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18
A12 GND Ground
A13 +5V +5 VDC
A14 AD24 Address 24
A15 AD27 Address 27
A16 GND Ground
A17 REQ2 Request 2 1
A18 CLKM
A19 CLK1 33 or 66 MHz Clock
A20 CLK2
A21 GND Ground
A22 CLK3
A23 CLK4
A24 +3,3V +3.3 VDC
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3
B3 +5V +5 VDC
B4 AD8 Address 8
B5 +3,3V +3.3 VDC
B6 AD14 Address 14
B7 PAR Parity
B8 +3,3V +3.3 VDC
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2
B11 V(I/O) +3.3 or +5 VDC
B12 AD21 Address 21
B13 +3,3V +3.3 VDC
B14 V(I/O) +3.3 or +5 VDC
B15 AD28 Address 28
B16 AD31 Address 31
B17 +3,3V +3.3 VDC
B18 GNT3 Grant 3
B19 RST# Reset
B20 NMI# Non Maskable Interrupt
B21 X6 Reserved (6)
B22 +5V +5 VDC :
B23 RSTIN#
B24 USB+ Universal Serial Bus (USB)(+)
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground
C3 AD7 Address 7
C4 AD9 Address 9
C5 AD11 Address 11
C6 GND Ground
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground
C11 AD19 Address 19
C12 AD22 Address 22
C13 GND Ground
C14 AD25 Address 25
C15 GND Ground
C16 X1 Reserved (1)
C17 GNT2 Grant 2
C18 REQ4 Request 4 1
C19 SLEEP#/SDAT Sleep/Serial Data (I2C)
C20 X4 Reserved (4)
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC
C24 USB- Universal Serial Bus (USB)(-)
D1 AD0 Address 0
D2 AD4 Address 4
D3 C/BE0# Command, Byte Enable 0
D4 +3,3V +3.3 VDC
D5 AD12 Address 12
D6 AD15 Address 15
D7 V(I/O) +3.3 or +5 VDC
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16
D11 AD20 Address 20
D12 +5V +5 VDC
D13 +5V +5 VDC
D14 AD26 Address 26
D15 AD29 Address 29
D16 REQ1 Request 1 1
D17 REQ3 Request 3 1
D18 V(I/O) +3.3 or +5 VDC
D19 X2 Reserved (2)
D20 X5 Reserved (5)
D21 +3,3V +3.3 VDC
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)
E1 AD1 Address 1
E2 AD5 Address 5
E3 GND Ground
E4 M66EN Enable 66Mhz PCI-bus
E5 GND Ground
E6 C/BE1# Command, Byte Enable 1
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC
E9 IRDY# Initatior Ready 1
E10 AD17 Address 17
E11 GND Ground
E12 AD23 Address 23
E13 C/BE3# Command, Byte Enable 3
E14 GND Ground
E15 AD30 Address 30
E16 GNT1 Grant 1
E17 +5V +5 VDC
E18 GNT4 Grant 4
E19 X3 Reserved (3)
E20 GND Ground
E21 INTC# Interrupt C 1
E22 -12V -12 VDC
E23 +12V +12 VDC
E24 VBATT

1 = Pullup resistor of 2,7 kW on the System Slot (CPU).

Card Slot (Middle)

PinNameDescriptionNote
A1 +3,3V +3.3 VDC
A2 AD2 Address 2
A3 AD6 Address 6
A4 GND Ground
A5 AD10 Address 10
A6 AD13 Address 13
A7 GND Ground
A8 SDONE Snoop Done 1
A9 GND Ground
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18
A12 GND Ground
A13 +5V +5 VDC
A14 AD24 Address 24
A15 AD27 Address 27
A16 GND Ground
A17 IDSEL0 IDSEL0 1
A18 GND Ground
A19 CLK1 33 or 66 MHz Clock
A20 GND Ground
A21 GND Ground
A22 GND Ground
A23 GND Ground
A24 +3,3V +3.3 VDC
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3
B3 +5V +5 VDC
B4 AD8 Address 8
B5 +3,3V +3.3 VDC
B6 AD14 Address 14
B7 PAR Parity
B8 +3,3V +3.3 VDC
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2
B11 V(I/O) +3.3 or +5 VDC
B12 AD21 Address 21
B13 +3,3V +3.3 VDC
B14 V(I/O) +3.3 or +5 VDC
B15 AD28 Address 28
B16 AD31 Address 31
B17 +3,3V +3.3 VDC
B18 GND Ground
B19 RST# Reset
B20 NMI# Non Maskable Interrupt
B21 X6 Reserved (6)
B22 +5V +5 VDC :
B23 RSTIN#
B24 USB+ Universal Serial Bus (USB)(+)
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground
C3 AD7 Address 7
C4 AD9 Address 9
C5 AD11 Address 11
C6 GND Ground
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground
C11 AD19 Address 19
C12 AD22 Address 22
C13 GND Ground
C14 AD25 Address 25
C15 GND Ground
C16 X1 Reserved (1)
C17 IDSEL1 Initialization Device Select 1
C18 GND Ground
C19 SLEEP#/SDAT Sleep/Serial Data (I2C)
C20 X4 Reserved (4)
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC
C24 USB- Universal Serial Bus (USB)(-)
D1 AD0 Address 0
D2 AD4 Address 4
D3 C/BE0# Command, Byte Enable 0
D4 +3,3V +3.3 VDC
D5 AD12 Address 12
D6 AD15 Address 15
D7 V(I/O) +3.3 or +5 VDC
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16
D11 AD20 Address 20
D12 +5V +5 VDC
D13 +5V +5 VDC
D14 AD26 Address 26
D15 AD29 Address 29
D16 REQ1 Request 1 1
D17 IDSEL2 Initialization Device Select 2
D18 V(I/O) +3.3 or +5 VDC
D19 X2 Reserved (2)
D20 X5 Reserved (5)
D21 +3,3V +3.3 VDC
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)
E1 AD1 Address 1
E2 AD5 Address 5
E3 GND Ground
E4 M66EN Enable 66Mhz PCI-bus
E5 GND Ground
E6 C/BE1# Command, Byte Enable 1
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC
E9 IRDY# Initatior Ready 1
E10 AD17 Address 17
E11 GND Ground
E12 AD23 Address 23
E13 C/BE3# Command, Byte Enable 3
E14 GND Ground
E15 AD30 Address 30
E16 GNT1 Grant 1
E17 +5V +5 VDC
E18 GNT4 Grant 4
E19 X3 Reserved (3)
E20 GND Ground
E21 INTC# Interrupt C 1
E22 -12V -12 VDC
E23 +12V +12 VDC
E24 VBATT

1 = Pullup resistor of 2,7 kW on the System Slot (CPU).

64-bit PCI (Top)

PinNameDescriptionNote
A1 GND Ground
A2 X10 Reserved (10)
A3 AD35 Address 35 2
A4 AD38 Address 38 2
A5 AD42 Address 42 2
A6 V(I/O) +3.3 or +5 VDC
A7 V(I/O) +3.3 or +5 VDC
A8 AD52 Address 52 2
A9 AD56 Address 56 2
A10 AD60 Address 60 2
A11 AD63 Address 63 2
A12 GND Ground
B1 X7 Reserved (7)
B2 GND Ground
B3 AD36 Address 36 2
B4 AD39 Address 39 2
B5 AD43 Address 43 2
B6 AD46 Address 46 2
B7 AD49 Address 49 2
B8 AD53 Address 53 2
B9 AD57 Address 57 2
B10 AD61 Address 61 2
B11 GND Ground
B12 C/BE6# Command, Byte Enable 6 2
C1 X8 Reserved (8)
C2 AD32 Address 32 2
C3 GND Ground
C4 AD40 Address 40 2
C5 AD44 Address 44 2
C6 GND Ground
C7 GND Ground
C8 AD54 Address 54 2
C9 AD58 Address 58 2
C10 GND Ground
C11 PAR64 Parity 64 ??? 2
C12 C/BE7# Command, Byte Enable 7 2
D1 X9 Reserved (9)
D2 AD33 Address 33 2
D3 AD37 Address 37 2
D4 GND Ground
D5 AD45 Address 45 2
D6 AD47 Address 47 2
D7 AD50 Address 50 2
D8 AD55 Address 55 2
D9 GND Ground
D10 AD62 Address 62 2
D11 C/BE4# Command, Byte Enable 4 2
D12 X11 Reserved (11)
E1 GND Ground
E2 AD34 Address 34 2
E3 V(I/O) +3.3 or +5 VDC
E4 AD41 Address 41 2
E5 GND Ground
E6 AD48 Address 48 2
E7 AD51 Address 51 2
E8 GND Ground
E9 AD59 Address 59 2
E10 V(I/O) +3.3 or +5 VDC
E11 C/BE5# Command, Byte Enable 5 2
E12 X12 Reserved (12)

2 = Pullup resistor of 2,7 kW (5V bus system) or 8,2 kW (3,3V bus system) on the backplane.

ISA96/AT96 (Bottom)

PinNameDescriptionNote
A1 RSTDRV
A2 IRQ9 Interrupt 9
A3 SD11 Data 11
A4 SD9 Data 9
A5 IOCHRDY 1
A6 IOW# I/O Write
A7 SA15 Address 15
A8 CLK Clock
A9 SA10 Address 10
A10 SA7 Address 7
A11 T/C
A12 SA2 Address 2
B1 SD15 Data 15
B2 SD13 Data 13
B3 SD3 Data 3
B4 SD1 Data 1
B5 SMEMW# System Memory Write
B6 SA18 Address 18
B7 SA14 Address 14
B8 DACK6# DMA Acknowledge 6
B9 SA9 Address 9
B10 IRQ3 Interrupt 3
B11 IOCS16# I/O 16-bit chip select 1
B12 SA1 Address 1
C1 SD7 Data 7
C2 SD5 Data 5
C3 SD10 Data 10
C4 SD8 Data 8
C5 AEN Address Enable
C6 IOR# I/O Read
C7 SA13 Address 13
C8 SA11 Address 11
C9 IRQ5 Interrupt 5
C10 SA6 Address 6
C11 SA4 Address 4
C12 IRQ11 Interrupt 11
D1 SD14 Data 14
D2 SD12 Data 12
D3 SD2 Data 2
D4 SD0 Data 0
D5 SMEMR# System Memory Read
D6 SA17 Address 17
D7 REF#
D8 IRQ7 Interrupt 7
D9 SA8 Address 8
D10 MCS16# 1
D11 BALE
D12 SA0 Address 0
E1 SD6 Data 6
E2 SD4 Data 4
E3 0WS 1
E4 SBHE#
E5 SA19 Address 19
E6 SA16 Address 16
E7 SA12 Address 12
E8 DRQ6 DMA Request 6
E9 IRQ4 Interrupt 4
E10 SA5 Address 5
E11 SA3 Address 3
E12 IRQ10 Interrupt 10

1 = Pullup resistor must be integrated into the System Slot (CPU).

VMEbus (Bottom)

PinNameDescription
A1 D0 Data 0
A2 D2 Data 2
A3 D12 Data 12
A4 D7 Data 7
A5 DS1#
A6 BR3#
A7 AM1
A8 AM3
A9 IACKOUT#
A10 A14 Address 14
A11 A12 Address 12
A12 A10 Address 10
B1 BBSY#
B2 D10 Data 10
B3 D5 Data 5
B4 D15 Data 15
B5 SYSRES#
B6 A23 Address 23
B7 A21 Address 21
B8 A19 Address 19
B9 A16 Address 16
B10 A6 Address 6
B11 A4 Address 4
B12 A2 Address 2
C1 D8 Data 8
C2 D3 Data 3
C3 D13 Data 13
C4 SYSCLK
C5 DS0#
C6 DTACK#
C7 AS#
C8 IACK#
C9 AM4
C10 A13 Address 13
C11 A11 Address 11
C12 A9 Address 9
D1 D1 Data 1
D2 D11 Data 11
D3 D6 Data 6
D4 BG3OUT#
D5 WR# Write
D6 AM0
D7 AM2
D8 A18 Address 18
D9 A15 Address 15
D10 A5 Address 5
D11 A3 Address 3
D12 A1 Address 1
E1 D9 Data 9
E2 D4 Data 4
E3 D14 Data 14
E4 BERR# Bus Error
E5 AM5
E6 A22 Address 22
E7 A20 Address 20
E8 A17 Address 17
E9 A7 Address 7
E10 IRQ5# Interrupt 5
E11 IRQ3# Interrupt 3
E12 A8 Address 8

ECB (Bottom)

PinNameDescription
A1 D5 Data 5
A2 D2 Data 2
A3 A4 Data 4
A4 A7 Address 7
A5 BAI
A6 2F
A7 A10 Address 10
A8 INT#
A9 VCMOS
A10 PWRCLR#
A11 A13 Address 13
A12 RESET# Reset
B1 D0 Data 0
B2 D4 Data 4
B3 A1 Address 1
B4 WAIT#
B5 A17 Address 17
B6 IEO
B7 n/c Not connected
B8 DMARDY
B9 RD# Read
B10 IORQ#
B11 ?
B12 n/c Not connected
C1 D6 Data 6
C2 A0 Address 0
C3 A5 Address 5
C4 A16 Address 16
C5 A18 Address 18
C6 BAO
C7 M1#
C8 WR#
C9 n
C10 A12 Address 12
C11 A9 Address 9
C12 n/c Not connected
D1 D7 Data 7
D2 A2 Address 2
D3 A8 Address 8
D4 BUSRQ#
D5 A19 Address 19
D6 A11 Address 11
D7 NMI# Non Maskable Interrupt
D8 PF
D9 HALT#
D10 RFSH#
D11 MRQ#
D12 n/c Not connected
E1 D3 Data 3
E2 A3 Address 3
E3 A6 Address 6
E4 IEI
E5 D1 Data 1
E6 A14 Address 14
E7 n/c Not connected
E8 n/c Not connected
E9 DESLCT#
E10 A15 Address 15
E11 BUSAK#
E12 n/c Not connected

SMP16 (Bottom)

PinNameDescription
A1 NMI# Non Maskable Interrupt
A2 IRQ0# Interrupt 0
A3 D11 Data 11
A4 D9 Data 9
A5 RDYIN
A6 IOW#
A7 A15 Address 15
A8 CLK
A9 A10 Address 10
A10 A7 Address 7
A11 TC/EOP#
A12 A2 Address 2
B1 D15 Data 15
B2 D13 Data 13
B3 D3 Data 3
B4 D1 Data 1
B5 MEMW#
B6 A18 Address 18
B7 A14 Address 14
B8 DACKx#
B9 A9 Address 9
B10 IRQ3# Interrupt 3
B11 IOCS16#
B12 A1 Address 1
C1 D7 Data 7
C2 D5 Data 5
C3 D10 Data 10
C4 D8 Data 8
C5 BUSEN
C6 IOR#
C7 A13 Address 13
C8 A11 Address 11
C9 IRQ1# Interrupt 1
C10 A6 Address 6
C11 A4 Address 4
C12 IRQ4# Interrupt 4
D1 D14 Data 14
D2 D12 Data 12
D3 D2 Data 2
D4 D0 Data 0
D5 MEMR#
D6 A17 Address 17
D7 INTA#
D8 INT#
D9 A8 Address 8
D10 MECS16#
D11 ALE
D12 A0 Address 0
E1 D6 Data 6
E2 D4 Data 4
E3 MMIO#
E4 BHEN
E5 A19 Address 19
E6 A16 Address 16
E7 A12 Address 12
E8 DRQx#
E9 IRQ2# Interrupt 2
E10 A5 Address 5
E11 A3 Address 3
E12 IRQ5# Interrupt 5

Floppy/EIDE (Bottom)

PinNameDescription
A1 FDSEL1 Floppy Select 1
A2 FDSEL0 Floppy Select 0
A3 FDME1 Floppy ?
A4 DIR Floppy Direction
A5 STEP Floppy Step
A6 WRDATA Floppy Write Data
A7 WE Floppy Write?
A8 TRK0 Floppy Track 0
A9 WP Floppy Write?
A10 RDDATA Floppy ?
A11 HDSEL Floppy HD Select
A12 DSKCHG Floppy DiskChange
B1 DRVDEN1 ?
B2 DRVDEN0 ?
B3 IDECS3P# IDE ?
B4 IDEA2 IDE ?
B5 IDEIRQS IDE ?
B6 IDEPUS IDE ?
B7 IDEDRQP IDE ?
B8 IDED14 IDE Data 14
B9 IDED8 IDE Data 8
B10 IDED6 IDE Data 6
B11 IDED11 IDE Data 11
B12 IDED3 IDE Data 3
C1 FDME0 Floppy Me?
C2 INDX Floppy Index
C3 IDECS3S# IDE ?
C4 IDEA0 IDE ?
C5 IDEDAKS# IDE ?
C6 IDEIOR# IDE ?
C7 IDEDRQS IDE ?
C8 IDED1 IDE Data 1
C9 #IDERST IDE ?
C10 IDED10 IDE Data 10
C11 IDED4 IDE Data 4
C12 IDED2 IDE Data 2
D1 IDELEDS# IDE LED ?
D2 IDELEDP# IDE LED ?
D3 IDECS1S# IDE ?
D4 IDEIRQP IDE ?
D5 IDEPUP IDE Pull Up ?
D6 IDEIOW# IDE ?
D7 IDED15 IDE Data 15
D8 IDED13 IDE Data 13
D9 IDED7 IDE Data 7
D10 GND Ground
D11 GND Ground
D12 GND Ground
E1 GND Ground
E2 GND Ground
E3 IDECS1P# IDE ?
E4 IDEA1 IDE ?
E5 IDEDAKP# IDE ?
E6 IDEIORDY IDE ?
E7 IDED0 IDE Data 0
E8 IDED12 IDE Data 12
E9 IDED9 IDE Data 9
E10 IDED5 IDE Data 5
E11 GND Ground
E12 GND Ground

SCSI (Bottom)

PinNameDescription
A1 TERM
A2 GND Ground
A3 I/O#
A4 REQ#
A5 ATN#
A6 D8 Data 8
A7 D9 Data 9
A8 D10 Data 10
A9 D2 Data 2
A10 D4 Data 4
A11 DP0
A12 GND Ground
B1 TERM
B2 GND Ground
B3 GND Ground
B4 GND Ground
B5 GND Ground
B6 GND Ground
B7 GND Ground
B8 GND Ground
B9 GND Ground
B10 GND Ground
B11 GND Ground
B12 GND Ground
C1 TERM
C2 GND Ground
C3 C/D#
C4 MSG#
C5 ACK#
C6 D12 Data 12
C7 DP1 Data P1
C8 D13 Data 13
C9 D1 Data 1
C10 D5 Data 5
C11 D7 Data 7
C12 GND Ground
D1 TERM
D2 GND Ground
D3 GND Ground
D4 GND Ground
D5 GND Ground
D6 GND Ground
D7 GND Ground
D8 GND Ground
D9 GND Ground
D10 GND Ground
D11 GND Ground
D12 GND Ground
E1 TERM
E2 GND Ground
E3 SEL#
E4 RST#
E5 BSY#
E6 D14 Data 14
E7 D15 Data 15
E8 D11 Data 11
E9 D0 Data 0
E10 D3 Data 3
E11 D6 Data 6
E12 GND Ground
 

CompactPCI

PCI=Peripheral Component Interconnect.
CompactPCI is a a version of PCI adapted for industrial and/or embedded applications.

NOT DRAWN YET (At the backplane)
NOT DRAWN YET (At the device (card))

7x47 PIN (IEC917 and IEC1076-4-101) CONNECTOR at the backplane.
7x47 PIN (IEC917 and IEC1076-4-101) CONNECTOR at the device (card).

PinNameDescription
Z1 GND Ground
Z2 GND Ground
Z3 GND Ground
Z4 GND Ground
Z5 GND Ground
Z6 GND Ground
Z7 GND Ground
Z8 GND Ground
Z9 GND Ground
Z10 GND Ground
Z11 GND Ground
Z12 KEY Keyed (no pin)
Z13 KEY Keyed (no pin)
Z14 KEY Keyed (no pin)
Z15 GND Ground
Z16 GND Ground
Z17 GND Ground
Z18 GND Ground
Z19 GND Ground
Z20 GND Ground
Z21 GND Ground
Z22 GND Ground
Z23 GND Ground
Z24 GND Ground
Z25 GND Ground
Z26 GND Ground
Z27 GND Ground
Z28 GND Ground
Z29 GND Ground
Z30 GND Ground
Z31 GND Ground
Z32 GND Ground
Z33 GND Ground
Z34 GND Ground
Z35 GND Ground
Z36 GND Ground
Z37 GND Ground
Z38 GND Ground
Z39 GND Ground
Z40 GND Ground
Z41 GND Ground
Z42 GND Ground
Z43 GND Ground
Z44 GND Ground
Z45 GND Ground
Z46 GND Ground
Z47 GND Ground
A1 5V +5 VDC
A2 TCK Test Clock
A3 INTA# Interrupt A
A4 BRSV Bused Reserved (don't use)
A5 BRSV Bused Reserved (don't use)
A6 REQ# Request PCI transfer
A7 AD(30) Address/Data 30
A8 AD(26) Address/Data 26
A9 C/BE(3)# Command: Byte Enable
A10 AD(21) Address/Data 21
A11 AD(18) Address/Data 18
A12 KEY Keyed (no pin)
A13 KEY Keyed (no pin)
A14 KEY Keyed (no pin)
A15 3.3V +3.3 VDC
A16 DEVSEL# Device Select
A17 3.3V +3.3 VDC
A18 SERR# System Error
A19 3.3V +3.3 VDC
A20 AD(12) Address/Data 12
A21 3.3V +3.3 VDC
A22 AD(7) Address/Data 7)
A23 3.3V +3.3 VDC
A24 AD(1) Address/Data 1)
A25 5V +5 VDC
A26 CLK1 Clock ?? MHz
A27 CLK2 Clock ?? MHz
A28 CLK4 Clock ?? MHz
A29 V(I/O) +3.3 VDC or +5 VDC
A30 C/BE(5)# Command: Byte Enable
A31 AD(63) Address/Data 63
A32 AD(59) Address/Data 59
A33 AD(56) Address/Data 56
A34 AD(52) Address/Data 52
A35 AD(49) Address/Data 49
A36 AD(45) Address/Data 45
A37 AD(42) Address/Data 42
A38 AD(38) Address/Data 38
A39 AD(35) Address/Data 35
A40 BRSV Bused Reserved (don't use)
A41 BRSV Bused Reserved (don't use)
A42 BRSV Bused Reserved (don't use)
A43 USR User Defined
A44 USR User Defined
A45 USR User Defined
A46 USR User Defined
A47 USR User Defined
B1 -12V -12 VDC
B2 5V +5 VDC
B3 INTB# Interrupt B
B4 GND Ground
B5 BRSV Bused Reserved (don't use)
B6 GND Ground
B7 AD(29) Address/Data 29
B8 GND Ground
B9 IDSEL Initialization Device Select
B10 GND Ground
B11 AD(17) Address/Data 17
B12 KEY Keyed (no pin)
B13 KEY Keyed (no pin)
B14 KEY Keyed (no pin)
B15 FRAME# Address or Data phase
B16 GND Ground
B17 SDONE Snoop Done
B18 GND Ground
B19 AD(15) Address/Data 15
B20 GND Ground
B21 AD(9) Address/Data 9)
B22 GND Ground
B23 AD(4) Address/Data 4)
B24 5V +5 VDC
B25 REQ64#
B26 GND Ground
B27 CLK3 Clock ?? MHz
B28 GND Ground
B29 BRSV Bused Reserved (don't use)
B30 GND Ground
B31 AD(62) Address/Data 62
B32 GND Ground
B33 AD(55) Address/Data 55
B34 GND Ground
B35 AD(48) Address/Data 48
B36 GND Ground
B37 AD(41) Address/Data 41
B38 GND Ground
B39 AD(34) Address/Data 34
B40 GND Ground
B41 BRSV Bused Reserved (don't use)
B42 GND Ground
B43 USR User Defined
B44 USR User Defined
B45 USR User Defined
B46 USR User Defined
B47 USR User Defined
C1 TRST# Test Logic Reset
C2 TMS Test Mode Select
C3 INTC# Interrupt C
C4 V(I/O) +3.3 VDC or +5 VDC
C5 RST Reset
C6 3.3V +3.3 VDC
C7 AD(28) Address/Data 28
C8 V(I/O) +3.3 VDC or +5 VDC
C9 AD(23) Address/Data 23
C10 3.3V +3.3 VDC
C11 AD(16) Address/Data 16
C12 KEY Keyed (no pin)
C13 KEY Keyed (no pin)
C14 KEY Keyed (no pin)
C15 IRDY# Initiator Ready
C16 V(I/O) +3.3 VDC or +5 VDC
C17 SBO# Snoop Backoff
C18 3.3V +3.3 VDC
C19 AD(14) Address/Data 14
C20 V(I/O) +3.3 VDC or +5 VDC
C21 AD(8) Address/Data 8)
C22 3.3V +3.3 VDC
C23 AD(3) Address/Data 3)
C24 V(I/O) +3.3 VDC or +5 VDC
C25 BRSV Bused Reserved (don't use)
C26 REQ1# Request PCI transfer
C27 SYSEN#
C28 GNT3# Grant
C29 C/BE(7) Command: Byte Enable
C30 V(I/O) +3.3 VDC or +5 VDC
C31 AD(61) Address/Data 61
C32 V(I/O) +3.3 VDC or +5 VDC
C33 AD(54) Address/Data 54
C34 V(I/O) +3.3 VDC or +5 VDC
C35 AD(47) Address/Data 47
C36 V(I/O) +3.3 VDC or +5 VDC
C37 AD(40) Address/Data 40
C38 V(I/O) +3.3 VDC or +5 VDC
C39 AD(33) Address/Data 33
C40 FAL# Power Supply Status FAL (CompactPCI specific)
C41 DEG# Power Supply Status DEG (CompactPCI specific)
C42 PRST# Push Button Reset (CompactPCI specific)
C43 USR User Defined
C44 USR User Defined
C45 USR User Defined
C46 USR User Defined
C47 USR User Defined
D1 +12V +12 VDC
D2 TDO Test Data Output
D3 5V +5 VDC
D4 INTP
D5 GND Ground
D6 CLK
D7 GND Ground
D8 AD(25) Address/Data 25
D9 GND Ground
D10 AD(20) Address/Data 20
D11 GND Ground
D12 KEY Keyed (no pin)
D13 KEY Keyed (no pin)
D14 KEY Keyed (no pin)
D15 GND Ground
D16 STOP# Stop transfer cycle
D17 GND Ground
D18 PAR Parity for AD0-31 & C/BE0-3
D19 GND Ground
D20 AD(11) Address/Data 11
D21 M66EN
D22 AD(6) Address/Data 6)
D23 5V +5 VDC
D24 AD(0) Address/Data 0)
D25 3.3V +3.3 VDC
D26 GNT1# Grant
D27 GNT2# Grant
D28 REQ4# Request PCI transfer
D29 GND Ground
D30 C/BE(4)# Command: Byte Enable
D31 GND Ground
D32 AD(58) Address/Data 58
D33 GND Ground
D34 AD(51) Address/Data 51
D35 GND Ground
D36 AD(44) Address/Data 44
D37 GND Ground
D38 AD(37) Address/Data 37
D39 GND Ground
D40 REQ5# Request PCI transfer
D41 GND Ground
D42 REQ6# Request PCI transfer
D43 USR User Defined
D44 USR User Defined
D45 USR User Defined
D46 USR User Defined
D47 USR User Defined
E1 5V +5 VDC
E2 TDI Test Data Input
E3 INTD# Interrupt D
E4 INTS
E5 GNT# Grant
E6 AD(31) Address/Data 31
E7 AD(27) Address/Data 27
E8 AD(24) Address/Data 24
E9 AD(22) Address/Data 22
E10 AD(19) Address/Data 19
E11 C/BE(2)# Command: Byte Enable
E12 KEY Keyed (no pin)
E13 KEY Keyed (no pin)
E14 KEY Keyed (no pin)
E15 TRDY# Target Ready
E16 LOCK# Lock resource
E17 PERR# Parity Error
E18 C/BE(1)# Command: Byte Enable
E19 AD(13) Address/Data 13
E20 AD(10) Address/Data 10
E21 C/BE(0)# Command: Byte Enable
E22 AD(5) Address/Data 5)
E23 AD(2) Address/Data 2)
E24 ACK64#
E25 5V +5 VDC
E26 REQ2# Request PCI transfer
E27 REQ3# Request PCI transfer
E28 GNT4# Grant
E29 C/BE(6)# Command: Byte Enable
E30 PAR64
E31 AD(60) Address/Data 60
E32 AD(57) Address/Data 57
E33 AD(53) Address/Data 53
E34 AD(50) Address/Data 50
E35 AD(46) Address/Data 46
E36 AD(43) Address/Data 43
E37 AD(39) Address/Data 39
E38 AD(36) Address/Data 36
E39 AD(32) Address/Data 32
E40 GNT5# Grant
E41 BRSV Bused Reserved (don't use)
E42 GNT6# Grant
E43 USR User Defined
E44 USR User Defined
E45 USR User Defined
E46 USR User Defined
E47 USR User Defined
F1 GND Ground
F2 GND Ground
F3 GND Ground
F4 GND Ground
F5 GND Ground
F6 GND Ground
F7 GND Ground
F8 GND Ground
F9 GND Ground
F10 GND Ground
F11 GND Ground
F12 KEY Keyed (no pin)
F13 KEY Keyed (no pin)
F14 KEY Keyed (no pin)
F15 GND Ground
F16 GND Ground
F17 GND Ground
F18 GND Ground
F19 GND Ground
F20 GND Ground
F21 GND Ground
F22 GND Ground
F23 GND Ground
F24 GND Ground
F25 GND Ground
F26 GND Ground
F27 GND Ground
F28 GND Ground
F29 GND Ground
F30 GND Ground
F31 GND Ground
F32 GND Ground
F33 GND Ground
F34 GND Ground
F35 GND Ground
F36 GND Ground
F37 GND Ground
F38 GND Ground
F39 GND Ground
F40 GND Ground
F41 GND Ground
F42 GND Ground
F43 GND Ground
F44 GND Ground
F45 GND Ground
F46 GND Ground
F47 GND Ground
 

VESA LocalBus (VLB)

VLB=VESA Local Bus.
VESA=Video Electronics Standards Association.

58 PIN EDGE CONNECTOR MALE (At the card)
58 PIN EDGE CONNECTOR FEMALE (At the computer)

58 PIN EDGE CONNECTOR MALE at the card.
58 PIN EDGE CONNECTOR FEMALE at the computer.

PinNameDescription
A1 D1 Data 1
A2 D3 Data 3
A3 GND Ground
A4 D5 Data 5
A5 D7 Data 7
A6 D9 Data 9
A7 D11 Data 11
A8 D13 Data 13
A9 D15 Data 15
A10 GND Ground
A11 D17 Data 17
A12 Vcc +5 VDC
A13 D19 Data 19
A14 D21 Data 21
A15 D23 Data 23
A16 D25 Data 25
A17 GND Ground
A18 D27 Data 27
A19 D29 Data 2
A20 D31 Data 31
A21 A30 Address 30
A22 A28 Address 28
A23 A26 Address 26
A24 GND Ground
A25 A24 Address 24
A26 A22 Address 22
A27 VCC +5 VDC
A28 A20 Address 20
A29 A18 Address 18
A30 A16 Address 16
A31 A14 Address 14
A32 A12 Address 12
A33 A10 Address 10
A34 A8 Address 8
A35 GND Ground
A36 A6 Address 6
A37 A4 Address 4
A38 WBACK# Write Back
A39 BE0# Byte Enable 0
A40 VCC +5 VDC
A41 BE1# Byte Enable 1
A42 BE2# Byte Enable 2
A43 GND Ground
A44 BE3# Byte Enable 3
A45 ADS# Address Strobe
A48 LRDY# Local Ready
A49 LDEV Local Device
A50 LREQ Local Request
A51 GND Ground
A52 LGNT Local Grant
A53 VCC +5 VDC
A54 ID2 Identification 2
A55 ID3 Identification 3
A56 ID4 Identification 4
A57 LKEN#
A58 LEADS# Local Enable Address Strobe
B1 D0 Data 0
B2 D2 Data 2
B3 D4 Data 4
B4 D6 Data 6
B5 D8 Data 8
B6 GND Ground
B7 D10 Data 10
B8 D12 Data 12
B9 VCC +5 VDC
B10 D14 Data 14
B11 D16 Data 16
B12 D18 Data 18
B13 D20 Data 20
B14 GND Ground
B15 D22 Data 22
B16 D24 Data 24
B17 D26 Data 26
B18 D28 Data 28
B19 D30 Data 30
B20 VCC +5 VDC
B21 A31 Address 31
B22 GND Ground
B23 A29 Address 29
B24 A27 Address 27
B25 A25 Address 25
B26 A23 Address 23
B27 A21 Address 21
B28 A19 Address 19
B29 GND Ground
B30 A17 Address 17
B31 A15 Address 15
B32 VCC +5 VDC
B33 A13 Address 13
B34 A11 Address 11
B35 A9 Address 9
B36 A7 Address 7
B37 A5 Address 5
B38 GND Ground
B39 A3 Address 3
B40 A2 Address 2
B41 n/c Not connected
B42 RESET# Reset
B43 DC# Data/Command
B44 M/IO# Memory/IO
B45 W/R# Write/Read
B48 RDYRTN# Ready Return
B49 GND Ground
B50 IRQ9 Interrupt 9
B51 BRDY# Burst Ready
B52 BLAST# Burst Last
B53 ID0 Identification 0
B54 ID1 Identification 1
B55 GND Ground
B56 LCLK Local Clock
B57 VCC +5 VDC
B58 LBS16# Local Bus Size 16
 

EISA (Technical)

This section is currently based soly on the work by Mark Sokos.

This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists and ametuers can design their own EISA compatible cards.

It is not intended to provide complete coverage of the EISA standard.

EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the ISA architecture, which is a standardized version of the bus originally developed by IBM for their PC computers. EISA is upwardly compatible, which means that cards originally designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the 16 bit bus (referred to as the AT bus, and also as the ISA bus), will work in an EISA slot. EISA specific cards will not work in an AT or an XT slot.

The EISA connector uses multiple rows of connectors. The upper row is the same as a regular ISA slot, and the lower row contains the EISA extension. The slot is keyed so that ISA cards cannot be inserted to the point where they connet with the EISA signals.

Signal Descriptions

+5, -5, +12, -12

Power supplies. -5 is often not implimented.

AEN

Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from responding to the I/O command lines during a DMA transfer.

BALE

Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should latch the LA bus on the falling edge of BALE.

BCLK

Bus Clock, 33% Duty Cycle. Frequency Varies. 8.33 MHz is specified as the maximum, but many systems allow this clock to be set to 10 MHz and higher.

BE(x)

Byte Enable. Indicates to the slave device which bytes on the data bus contain valid data. A 16 bit transfer would assert BE0 and BE1, for example, but not BE2 or BE3.

CHCHK

Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu.

CHRDY

Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end the bus cycle. Holding this line low for too long can cause problems on some systems. CHRDY and NOWS should not be used simultaneously. This may cause problems with some bus controllers.

CMD

Command Phase. This signal indicates that the current bus cycle is in the command phase. After the start phase (see START), the data is transferred during the CMD phase. CMD remains asserted from the falling edge of START until the end of the bus cycle.

SD0-SD16

System Data lines. They are bidrectional and tri-state.

DAKx

DMA Acknowledge.

DRQx

DMA Request.

EX16

EISA Slave Size 16. This is used by the slave device to inform the bus master that it is capable of 16 bit transfers.

EX32

EISA Slave Size 32. This is used by the slave device to inform the bus master that it is capable of 32 bit transfers.

EXRDY

EISA Ready. If this signal is asserted, the cycle will end on the next rising edge of BCLK. The slave device drives this signal low to insert wait states.

IO16

I/O size 16. Generated by a 16 bit slave when addressed by a bus master.

IORC

I/O Read Command line.

IOWC

I/O Write Command line.

IRQx

Interrupt Request. IRQ2 has the highest priority.

LAxx

Latchable Address lines.

LOCK

Asserting this signal prevents other bus masters from requesting control of the bus.

MAKx

Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been granted.

MASTER16

16 bit bus master. Generated by the ISA bus master when initiating a bus cycle.

M/IO

Memory/Input-Output. This is used to indicate whether the current bus cycle is a memory or an I/O operation.

M16

Memory Access, 16 bit

MRDC

Memory Read Command line.

MREQx

Master Request for Slot x: This is a slot specific request for the device to become the bus master.

MSBURST

Master Burst. The bus master asserts this signal in response to SLBURST. This tells the slave device that the bus master is also capable of burst cycles.

MWTC

Memory Write Command line.

NOWS

No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both signals should not be active simultaneously.

OSC

Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies.

REFRESH

Refresh. Generated when the refresh logic is bus master.

RESDRV

This signal goes low when the machine is powered up. Driving it low will force a system reset.

SA0-SA19

System Address Lines, tri-state.

SBHE

System Bus High Enable, tristate. Indicates a 16 bit data transfer.

SLBURST

Slave Burst. The slave device uses this to indicate that it is capable of burst cycles. The bus master will respond with MSBURST if it is also capable of burst cycles.

SMRDC

Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area.

SMWTC

Standard Memory Write Commmand line. Indicates a memory write in the lower 1 MB area.

START

Start Phase. This signal is low when the current bus cycle is in the start phase. Address and M/IO signals are decoded during this phase. Data is transferred during the command phase (indicated by CMD).

TC

Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete.

W/R

Write or Read. Used to indicate if the current bus cycle is a read or a write operation.

 
 

EISA

EISA=Extended Industry Standard Architecture.
Developed by Compaq, AST, Zenith, Tandy...

+---------------------------------------------+
|            (component side)                 |
|                                             |
|___________ ISA-16bit __       ISA-8bit    __|
            |||||||||||  |||||||||||||||||||  A1(front)/B1(back)
             | | | | |    | | | | | | | | |  EISA: E1(front)/F1(back)
                   C1/D1
                  G1/H1
A,C,E,G=Component Side
A,B,F,H=Sold Side

NOT DRAWN YET (At the computer)

62+38 PIN EDGE CONNECTOR at the computer.

Pin Name Description
E1 CMD# Command Phase
E2 START# Start Phase
E3 EXRDY EISA Ready
E4 EX32# EISA Slave Size 32
E5 GND Ground
E6 KEY Access Key
E7 EX16# EISA Slave Size 16
E8 SLBURST# Slave Burst
E9 MSBURST# Master Burst
E10 W/R# Write/Read
E11 GND Ground
E12 RES Reserved
E13 RES Reserved
E14 RES Reserved
E15 GND Ground
E16 KEY Access Key
E17 BE1# Byte Enable 1
E18 LA31# Latchable Addressline 31
E19 GND Ground
E20 LA30# Latchable Addressline 30
E21 LA28# Latchable Addressline 28
E22 LA27# Latchable Addressline 27
E23 LA25# Latchable Addressline 25
E24 GND Ground
E25 KEY Access Key
E26 LA15 Latchable Addressline 15
E27 LA13 Latchable Addressline 13
E28 LA12 Latchable Addressline 12
E29 LA11 Latchable Addressline 11
E30 GND Ground
E31 LA9 Latchable Addressline 9
     
F1 GND Ground
F2 +5V +5 VDC
F3 +5V +5 VDC
F4 ---  
F5 ---  
F6 KEY Access Key
F7 ---  
F8 ---  
F9 +12V +12 VDC
F10 M/IO# Memory/Input-Output
F11 LOCK# Lock bus
F12 RES Reserved
F13 GND Ground
F14 RES Reserved
F15 BE3# Byte Enable 3
F16 KEY Access Key
F17 BE2# Byte Enable 2
F18 BE0# Byte Enable 0
F19 GND Ground
F20 +5V +5 VDC
F21 LA29# Latchable Addressline 29
F22 GND Ground
F23 LA26# Latchable Addressline 26
F24 LA24# Latchable Addressline 24
F25 KEY Access Key
F26 LA16 Latchable Addressline 16
F27 LA14 Latchable Addressline 14
F28 +5V +5 VDC
F29 +5V +5 VDC
F30 GND Ground
F31 LA10 Latchable Addressline 10
     
G1 LA7 Latchable Addressline 7
G2 GND Ground
G3 LA4 Latchable Addressline 4
G4 LA3 Latchable Addressline 3
G5 GND Ground
G6 KEY Access Key
G7 D17 Data 17
G8 D19 Data 19
G9 D20 Data 20
G10 D22 Data 22
G11 GND Ground
G12 D25 Data 25
G13 D26 Data 26
G14 D28 Data 28
G15 KEY Access Key
G16 GND Ground
G17 D30 Data 30
G18 D31 Data 31
G19 MREQx Master Request
     
H1 LA8 Latchable Addressline 8
H2 LA6 Latchable Addressline 6
H3 LA5 Latchable Addressline 5
H4 +5V +5 VDC
H5 LA2 Latchable Addressline 2
H6 KEY Access Key
H7 D16 Data 16
H8 D18 Data 18
H9 GND Ground
H10 D21 Data 21
H11 D23 Data 23
H12 D24 Data 24
H13 GND Ground
H14 D27 Data 27
H15 KEY Access Key
H16 D29 Data 29
H17 +5V +5 VDC
H18 +5V +5 VDC
H19 MAKx Master Acknowledge
 
 
 
 
Обратная связь

Наши партнеры

 

Опросы

Есть ли справедливость в жизни?
Конечно есть, уверен!
Вроде как должна быть, но...
Затрудняюсь ответить...
Какая справедливость? О чем Вы?
Эх.., нет правды на свете!

 

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