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VESA LocalBus (VLB) (Technical)

This section is currently based soly on the work by Mark Sokos.

This file is intended to provide a basic functional overview of the Vesa Local Bus, so that hobbyists and ametuers can design their own VLB compatible cards.

It is not intended to provide complete coverage of the VLB standard.

VLB Connectors are usually inline with ISA connectors, so that adapter cards may use both. However, the VLB is seperate, and does not need to connect to the ISA portion of the bus.

The 64 bit expansion of the bus (optional) does not add additional pins or connectors. Instead, it multiplexes the existing pins. The 32 bit VLB bus does not use the 64 bit signals shown in the above pinouts.

Signal Descriptions

A2-A31

Address Bus

ADS

Address Strobe

BE0-BE3

Byte Enable. Indicates that the 8 data lines corresponding to each signal will deliver valid data.

BLAST

Burst Last. Indicates a VLB Burst Cycle, which will complete with *BRDY. The VLB Burst cycle consists of an address phase followed by four data phases.

BRDY

Burst Ready. Indicates the end of the current burst transfer.

D0-D31

Data Bus. Valid bytes are indicated by *BE(x) signals.

D/C

Data/Command. Used with M/IO and W/R to indicate the type of cycle.

M/IOD/CW/R
0 0 0 INTA sequence
0 0 1 Halt/Special (486)
0 1 0 I/O Read
0 1 1 I/O Write
1 0 0 Instruction Fetch
1 0 1 Halt/Shutdown (386)
1 1 0 Memory Read
1 1 1 Memory Write

ID0-ID4

Identification Signals.

ID0ID1ID4CPUBus WidthBurst
0 0 0 (res)
0 0 1 (res)
0 1 0 486 16/32 Burst Possible
0 1 1 486 16/32 Read Burst
1 0 0 386 16/32 None
1 0 1 386 16/32 None
1 1 0 (res)
1 1 1 486 16/32/64 Read/Write Burst

ID2 Indicates wait: 0 = 1 wait cycle (min)
1 = no wait
ID3 Indicates bus speed: 0 = greater than 33.3 MHz
1 = less than 33.3 MHz

IRQ9

Interrupt Request. Connected to IRQ9 on ISA bus.This allows standalone VLB adapters (not connected to ISA portion of the bus) to have one IRQ.

LEADS

Local Enable Address Strobe. Set low by VLB master (not CPU). Also used for cache invalidation signal.

LBS16

Local Bus Size 16. Used by slave device to indicate that it has a transfer width of only 16 bits.

LCLK

Local Clock. Runs at the same frequency as the cpu, up to 50 MHz. 66 MHz is allowed for on-board devices.

LDEV

Local Device: When appropriate address and M/IO signals are present on the bus, the VLB device must pull this line low to indicate that it is a VLB device. The VLB controller will then use the VLB bus for the transfer.

LRDY

Local Ready. Indicates that the VLB device has completed the cycle. This signal is only used for single cycle transfers. *BRDY is used for burst transfers.

LGNT

Local Grant. Indicates that an *LREQ signal has been granted, and control is being transferred to the new VLB master.

LREQ

Local Request. Used by VLB Master to gain control of the bus.

M/IO

Memory/IO. See D/C for signal description.

RDYRTN

Ready Return. Indicates VLB cycle has been completed. May precede LRDY by one cycle.

RESET

Reset. Resets all VLB devices.

WBACK

Write Back.

64-bit Expansion Signals

ACK64

Acknowledge 64 bit transfer. Indicates that the device can perform the requested 64 bit transfer cycle.

BE4-BE7

Byte Enable. Indicates which bytes are valid (similar to BE0-BE3).

D32-D63

Upper 32 bits of data bus. Multiplexed with address bus.

LBS64

Local Bus Size 64 bits. Used by VLB Master to indicate that it desires a 64 bit transfer.

W/R

Write/Read. See D/C for signal description.

64 Bit Data Transfer Timing Diagram:

             Address         Data
             Phase           Phase
             _______         _______         _______
LCLK     ___|       |_______|       |_______|       |_______
         ____         ______________________________________
*ADS         |_______|
              _______________  _______________
A2-A31   -----------------
D34-D63         Address          Data D34-D63
              _______________  _______________
D/C      -----------------
M/IO, W/R      M/IO, W/R         Data D32-33
         _____                 _____________________________
*LDEV         |_______________|
         _____                 _____________________________
*LBS64        |_______________|
         ______                _____________________________
*ACK64         |______________|
                               _______________
D0-D31    ---------------------------------
          _____________________                _____________
LRDY                           |______________|
 

EISA (Technical)

This section is currently based soly on the work by Mark Sokos.

This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists and ametuers can design their own EISA compatible cards.

It is not intended to provide complete coverage of the EISA standard.

EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the ISA architecture, which is a standardized version of the bus originally developed by IBM for their PC computers. EISA is upwardly compatible, which means that cards originally designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the 16 bit bus (referred to as the AT bus, and also as the ISA bus), will work in an EISA slot. EISA specific cards will not work in an AT or an XT slot.

The EISA connector uses multiple rows of connectors. The upper row is the same as a regular ISA slot, and the lower row contains the EISA extension. The slot is keyed so that ISA cards cannot be inserted to the point where they connet with the EISA signals.

Signal Descriptions

+5, -5, +12, -12

Power supplies. -5 is often not implimented.

AEN

Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from responding to the I/O command lines during a DMA transfer.

BALE

Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should latch the LA bus on the falling edge of BALE.

BCLK

Bus Clock, 33% Duty Cycle. Frequency Varies. 8.33 MHz is specified as the maximum, but many systems allow this clock to be set to 10 MHz and higher.

BE(x)

Byte Enable. Indicates to the slave device which bytes on the data bus contain valid data. A 16 bit transfer would assert BE0 and BE1, for example, but not BE2 or BE3.

CHCHK

Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu.

CHRDY

Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end the bus cycle. Holding this line low for too long can cause problems on some systems. CHRDY and NOWS should not be used simultaneously. This may cause problems with some bus controllers.

CMD

Command Phase. This signal indicates that the current bus cycle is in the command phase. After the start phase (see START), the data is transferred during the CMD phase. CMD remains asserted from the falling edge of START until the end of the bus cycle.

SD0-SD16

System Data lines. They are bidrectional and tri-state.

DAKx

DMA Acknowledge.

DRQx

DMA Request.

EX16

EISA Slave Size 16. This is used by the slave device to inform the bus master that it is capable of 16 bit transfers.

EX32

EISA Slave Size 32. This is used by the slave device to inform the bus master that it is capable of 32 bit transfers.

EXRDY

EISA Ready. If this signal is asserted, the cycle will end on the next rising edge of BCLK. The slave device drives this signal low to insert wait states.

IO16

I/O size 16. Generated by a 16 bit slave when addressed by a bus master.

IORC

I/O Read Command line.

IOWC

I/O Write Command line.

IRQx

Interrupt Request. IRQ2 has the highest priority.

LAxx

Latchable Address lines.

LOCK

Asserting this signal prevents other bus masters from requesting control of the bus.

MAKx

Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been granted.

MASTER16

16 bit bus master. Generated by the ISA bus master when initiating a bus cycle.

M/IO

Memory/Input-Output. This is used to indicate whether the current bus cycle is a memory or an I/O operation.

M16

Memory Access, 16 bit

MRDC

Memory Read Command line.

MREQx

Master Request for Slot x: This is a slot specific request for the device to become the bus master.

MSBURST

Master Burst. The bus master asserts this signal in response to SLBURST. This tells the slave device that the bus master is also capable of burst cycles.

MWTC

Memory Write Command line.

NOWS

No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both signals should not be active simultaneously.

OSC

Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies.

REFRESH

Refresh. Generated when the refresh logic is bus master.

RESDRV

This signal goes low when the machine is powered up. Driving it low will force a system reset.

SA0-SA19

System Address Lines, tri-state.

SBHE

System Bus High Enable, tristate. Indicates a 16 bit data transfer.

SLBURST

Slave Burst. The slave device uses this to indicate that it is capable of burst cycles. The bus master will respond with MSBURST if it is also capable of burst cycles.

SMRDC

Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area.

SMWTC

Standard Memory Write Commmand line. Indicates a memory write in the lower 1 MB area.

START

Start Phase. This signal is low when the current bus cycle is in the start phase. Address and M/IO signals are decoded during this phase. Data is transferred during the command phase (indicated by CMD).

TC

Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete.

W/R

Write or Read. Used to indicate if the current bus cycle is a read or a write operation.

 
 
 
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