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Miniature Card (Technical)

This section is currently based soly on the Miniature Card specification v1.1.

Signal Descriptions:

A0-A24

Address A0 to A24 are the address bus lines that can address up to 32 Mwords (64 MBytes). The Miniature Card specification does not require the Miniature Card to decode the upper address lines. A 2 Mbyte Miniature Card that does not decode the upper address lines would repeat its address space every 2 Mbytes. Address 0h would access the same physical location as 200000h, 400000h, 600000h, etc.

D0-D15

Data lines D0 through D15 constitute the data bus. The data bus is composed of two bytes, the low byte D[7:0] and the high byte D[15:8].

OE#

OE# indicates that the current bus cycle is a read cycle.

WE#

WE# indicates that the current bus cycle is a write cycle.

VS1#

Voltage Sense 1 signal. The card grounds this signal to indicate it can operate at 3.3 Volts. This signal must either be connected to card GND or left open.

VS2#

Voltage Sense 2 signal. The card grounds this signal to indicate it can operate at x.x Volts (the value to be determined at a later date). This signal must either be connected to card GND or left open.

CEL#

CEL# enables the low byte of the data bus (D[7:0]) on the card. This signal is not used in DRAM cards.

CEH#

CEH# enables the high byte of the data bus (D[15:8]) on the card. This signal is not used in DRAM cards.

RAS#

RAS# strobes in the row address for DRAM cards.

CASL#

CASL# strobes in the low byte column address for DRAM cards.

CASH#

CASH# strobes in the high byte column address for DRAM cards.

RESET#

RESET# controls card initialization. When RESET# transitions from a low state to a high state, the Miniature Card must reset to a predetermined state.

BUSY#

BUSY# is a signal generated by the card to indicate the status of operations within the Miniature Card. When BUSY# is high, the Miniature Card is ready to accept the next command from the host. When BUSY# is low, the Miniature Card is busy and unable to accept some data operations from the host. For example, in Flash Miniature Cards the BUSY# signal is tied to the components RY/BY# signal. However, ROM Miniature Cards would always drive BUSY# high since the host will always be able to read from a ROM Miniature Card.

Vccr

Vccr provides a low current (refresh) voltage supply. Vccr is a feature used by DRAM Miniature Cards to "self-refresh" during "sleep" mode.

SDA

I2C: Serial Data/Address.

SCL

I2C: Serial Clock are used to read the attribute information structure (AIS) from the serial EEPROM in a DRAM card.

CD#

CD# is a grounded interface signal. After a Miniature Card has been inserted, CD# will be forced low. The card detect signal is located in the center of the second row of interface signals, and should be one of the last interface signals to connect to the host. Do not confuse CD# with CINS#. CINS# is an early card detect that is one of the first signals to connect to the host.

BS8#

BS8# is a signal driven by the host to indicate if the data bus is x8 or x16. An 8-bit host must drive BS8# low and tie the high byte data bus D[15:8] to the low byte data bus D[7:0]. A 16-bit host must drive this signal high.

GND

Ground

Vcc

Vcc is used to supply power to the card.

CINS#

CINS# is a grounded signal on the front of the Miniature Card that can be used for early detection of a card insertion. CINS# makes contact on the host when the front of the card is inserted into the socket, before the interface signals connect.

 

EISA (Technical)

This section is currently based soly on the work by Mark Sokos.

This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists and ametuers can design their own EISA compatible cards.

It is not intended to provide complete coverage of the EISA standard.

EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the ISA architecture, which is a standardized version of the bus originally developed by IBM for their PC computers. EISA is upwardly compatible, which means that cards originally designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the 16 bit bus (referred to as the AT bus, and also as the ISA bus), will work in an EISA slot. EISA specific cards will not work in an AT or an XT slot.

The EISA connector uses multiple rows of connectors. The upper row is the same as a regular ISA slot, and the lower row contains the EISA extension. The slot is keyed so that ISA cards cannot be inserted to the point where they connet with the EISA signals.

Signal Descriptions

+5, -5, +12, -12

Power supplies. -5 is often not implimented.

AEN

Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from responding to the I/O command lines during a DMA transfer.

BALE

Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should latch the LA bus on the falling edge of BALE.

BCLK

Bus Clock, 33% Duty Cycle. Frequency Varies. 8.33 MHz is specified as the maximum, but many systems allow this clock to be set to 10 MHz and higher.

BE(x)

Byte Enable. Indicates to the slave device which bytes on the data bus contain valid data. A 16 bit transfer would assert BE0 and BE1, for example, but not BE2 or BE3.

CHCHK

Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu.

CHRDY

Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end the bus cycle. Holding this line low for too long can cause problems on some systems. CHRDY and NOWS should not be used simultaneously. This may cause problems with some bus controllers.

CMD

Command Phase. This signal indicates that the current bus cycle is in the command phase. After the start phase (see START), the data is transferred during the CMD phase. CMD remains asserted from the falling edge of START until the end of the bus cycle.

SD0-SD16

System Data lines. They are bidrectional and tri-state.

DAKx

DMA Acknowledge.

DRQx

DMA Request.

EX16

EISA Slave Size 16. This is used by the slave device to inform the bus master that it is capable of 16 bit transfers.

EX32

EISA Slave Size 32. This is used by the slave device to inform the bus master that it is capable of 32 bit transfers.

EXRDY

EISA Ready. If this signal is asserted, the cycle will end on the next rising edge of BCLK. The slave device drives this signal low to insert wait states.

IO16

I/O size 16. Generated by a 16 bit slave when addressed by a bus master.

IORC

I/O Read Command line.

IOWC

I/O Write Command line.

IRQx

Interrupt Request. IRQ2 has the highest priority.

LAxx

Latchable Address lines.

LOCK

Asserting this signal prevents other bus masters from requesting control of the bus.

MAKx

Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been granted.

MASTER16

16 bit bus master. Generated by the ISA bus master when initiating a bus cycle.

M/IO

Memory/Input-Output. This is used to indicate whether the current bus cycle is a memory or an I/O operation.

M16

Memory Access, 16 bit

MRDC

Memory Read Command line.

MREQx

Master Request for Slot x: This is a slot specific request for the device to become the bus master.

MSBURST

Master Burst. The bus master asserts this signal in response to SLBURST. This tells the slave device that the bus master is also capable of burst cycles.

MWTC

Memory Write Command line.

NOWS

No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both signals should not be active simultaneously.

OSC

Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies.

REFRESH

Refresh. Generated when the refresh logic is bus master.

RESDRV

This signal goes low when the machine is powered up. Driving it low will force a system reset.

SA0-SA19

System Address Lines, tri-state.

SBHE

System Bus High Enable, tristate. Indicates a 16 bit data transfer.

SLBURST

Slave Burst. The slave device uses this to indicate that it is capable of burst cycles. The bus master will respond with MSBURST if it is also capable of burst cycles.

SMRDC

Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area.

SMWTC

Standard Memory Write Commmand line. Indicates a memory write in the lower 1 MB area.

START

Start Phase. This signal is low when the current bus cycle is in the start phase. Address and M/IO signals are decoded during this phase. Data is transferred during the command phase (indicated by CMD).

TC

Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete.

W/R

Write or Read. Used to indicate if the current bus cycle is a read or a write operation.

 
 
 
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