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Zorro II/III

100 PIN EDGE CONNECTOR (At the computer)

100 PIN EDGE CONNECTOR at the computer.

PinPhysical
Name
Zorro II
Name
Zorro III
Address Phase
Zorro III
Data Phase
1 Ground Ground Ground Ground
2 Ground Ground Ground Ground
3 Ground Ground Ground Ground
4 Ground Ground Ground Ground
5 +5VDC +5VDC +5VDC +5VDC
6 +5VDC +5VDC +5VDC +5VDC
7 /OWN /OWN /OWN /OWN
8 -5VDC -5VDC -5VDC -5VDC
9 /SLAVEn /SLAVEn /SLAVEn /SLAVEn
10 +12VDC +12VDC +12VDC +12VDC
11 /CFGOUTn /CFGOUTn /CFGOUTn /CFGOUTn
12 /CFGINn /CFGINn /CFGINn /CFGINn
13 Ground Ground Ground Ground
14 /C3 /C3 Clock /C3 Clock /C3 Clock
15 CDAC CDAC Clock CDAC Clock CDAC Clock
16 /C1 /C1 Clock /C1 Clock /C1 Clock
17 /CINH /OVR /CINH /CINH
18 /MTCR XRDY /MTCR /MTCR
19 /INT2 /INT2 /INT2 /INT2
20 -12VDC -12VDC -12VDC -12VDC
21 A5 A5 A5 A5
22 /INT6 /INT6 /INT6 /INT6
23 A6 A6 A6 A6
24 A4 A4 A4 A4
25 Ground Ground Ground Ground
26 A3 A3 A3 A3
27 A2 A2 A2 A2
28 A7 A7 A7 A7
29 /LOCK A1 /LOCK /LOCK
30 AD8 A8 A8 D0
31 FC0 FC0 FC0 FC0
32 AD9 A9 A9 D1
33 FC1 FC1 FC1 FC1
34 AD10 A10 A10 D2
35 FC2 FC2 FC2 FC2
36 AD11 A11 A11 D3
37 Ground Ground Ground Ground
38 AD12 A12 A12 D4
39 AD13 A13 A13 D5
40 Reserved (/EINT7) Reserved Reserved
41 AD14 A14 A14 D6
42 Reserved (/EINT5) Reserved Reserved
43 AD15 A15 A15 D7
44 Reserved (/EINT4) Reserved Reserved
45 AD16 A16 A16 D8
46 /BERR /BERR /BERR /BERR
47 AD17 A17 A17 D9
48 /MTACK (/VPA) /MTACK /MTACK
49 Ground Ground Ground Ground
50 E Clock E Clock E Clock E Clock
51 /DS0 (/VMA) /DS0 /DS0
52 AD18 A18 A18 D10
53 /RESET /RST /RESET /RESET
54 AD19 A19 A19 D11
55 /HLT /HLT /HLT /HLT
56 AD20 A20 A20 D12
57 AD22 A22 A22 D14
58 AD21 A21 A21 D13
59 AD23 A23 A23 D15
60 /BRn /BRn /BRn /BRn
61 Ground Ground Ground Ground
62 /BGACK /BGACK /BGACK /BGACK
63 AD31 D15 A31 D31
64 /BGn /BGn /BGn /BGn
65 AD30 D14 A30 D30
66 /DTACK /DTACK /DTACK /DTACK
67 AD29 D13 A29 D29
68 READ READ READ READ
69 AD28 D12 A28 D28
70 /DS2 /LDS /DS2 /DS2
71 AD27 D11 A27 D27
72 /DS3 /UDS /DS3 /DS3
73 Ground Ground Ground Ground
74 /CCS /AS /CCS /CCS
75 SD0 D0 Reserved D16
76 AD26 D10 A26 D26
77 SD1 D1 Reserved D17
78 AD25 D9 A25 D25
79 SD2 D2 Reserved D18
80 AD24 D8 A24 D24
81 SD3 D3 Reserved D19
82 SD7 D7 Reserved D23
83 SD4 D4 Reserved D20
84 SD6 D6 Reserved D22
85 Ground Ground Ground Ground
86 SD5 D5 Reserved D21
87 Ground Ground Ground Ground
88 Ground Ground Ground Ground
89 Ground Ground Ground Ground
90 Ground Ground Ground Ground
91 SenseZ3 Ground SenseZ3 SenseZ3
92 7M E7M 7M 7M
93 DOE DOE DOE DOE
94 /IORST /BUSRST /IORST /IORST
95 /BCLR /GBG /BCLR /BCLR
96 Reserved (/EINT1) Reserved Reserved
97 /FCS No Connect /FCS /FCS
98 /DS1 No Connect /DS1 /DS1
99 Ground Ground Ground Ground
100 Ground Ground Ground Ground
 

Miniature Card (Technical)

This section is currently based soly on the Miniature Card specification v1.1.

Signal Descriptions:

A0-A24

Address A0 to A24 are the address bus lines that can address up to 32 Mwords (64 MBytes). The Miniature Card specification does not require the Miniature Card to decode the upper address lines. A 2 Mbyte Miniature Card that does not decode the upper address lines would repeat its address space every 2 Mbytes. Address 0h would access the same physical location as 200000h, 400000h, 600000h, etc.

D0-D15

Data lines D0 through D15 constitute the data bus. The data bus is composed of two bytes, the low byte D[7:0] and the high byte D[15:8].

OE#

OE# indicates that the current bus cycle is a read cycle.

WE#

WE# indicates that the current bus cycle is a write cycle.

VS1#

Voltage Sense 1 signal. The card grounds this signal to indicate it can operate at 3.3 Volts. This signal must either be connected to card GND or left open.

VS2#

Voltage Sense 2 signal. The card grounds this signal to indicate it can operate at x.x Volts (the value to be determined at a later date). This signal must either be connected to card GND or left open.

CEL#

CEL# enables the low byte of the data bus (D[7:0]) on the card. This signal is not used in DRAM cards.

CEH#

CEH# enables the high byte of the data bus (D[15:8]) on the card. This signal is not used in DRAM cards.

RAS#

RAS# strobes in the row address for DRAM cards.

CASL#

CASL# strobes in the low byte column address for DRAM cards.

CASH#

CASH# strobes in the high byte column address for DRAM cards.

RESET#

RESET# controls card initialization. When RESET# transitions from a low state to a high state, the Miniature Card must reset to a predetermined state.

BUSY#

BUSY# is a signal generated by the card to indicate the status of operations within the Miniature Card. When BUSY# is high, the Miniature Card is ready to accept the next command from the host. When BUSY# is low, the Miniature Card is busy and unable to accept some data operations from the host. For example, in Flash Miniature Cards the BUSY# signal is tied to the components RY/BY# signal. However, ROM Miniature Cards would always drive BUSY# high since the host will always be able to read from a ROM Miniature Card.

Vccr

Vccr provides a low current (refresh) voltage supply. Vccr is a feature used by DRAM Miniature Cards to "self-refresh" during "sleep" mode.

SDA

I2C: Serial Data/Address.

SCL

I2C: Serial Clock are used to read the attribute information structure (AIS) from the serial EEPROM in a DRAM card.

CD#

CD# is a grounded interface signal. After a Miniature Card has been inserted, CD# will be forced low. The card detect signal is located in the center of the second row of interface signals, and should be one of the last interface signals to connect to the host. Do not confuse CD# with CINS#. CINS# is an early card detect that is one of the first signals to connect to the host.

BS8#

BS8# is a signal driven by the host to indicate if the data bus is x8 or x16. An 8-bit host must drive BS8# low and tie the high byte data bus D[15:8] to the low byte data bus D[7:0]. A 16-bit host must drive this signal high.

GND

Ground

Vcc

Vcc is used to supply power to the card.

CINS#

CINS# is a grounded signal on the front of the Miniature Card that can be used for early detection of a card insertion. CINS# makes contact on the host when the front of the card is inserted into the socket, before the interface signals connect.

 
 
 
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