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IndustrialPCI (IPCI)

PCI=Peripheral Component Interconnect.
IndustrialPCI is a a version of PCI adapted for industrial and/or embedded applications.

The IPCI connector has three parts:

  • Optional 60 pin PCI 64 bit extension (Top)
  • Mandatory 120 pin PCI 32 bit (Middle)
  • Optional 60 pin Custom I/O (Bottom)

UNKNOWN (At the backplane)
UNKNOWN (At the device (card))

UNKNOWN CONNECTOR at the backplane.
UNKNOWN CONNECTOR at the device (card).

System Slot (Middle)

PinNameDescriptionNote
A1 +3,3V +3.3 VDC
A2 AD2 Address 2
A3 AD6 Address 6
A4 GND Ground
A5 AD10 Address 10
A6 AD13 Address 13
A7 GND Ground
A8 SDONE Snoop Done 1
A9 GND Ground
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18
A12 GND Ground
A13 +5V +5 VDC
A14 AD24 Address 24
A15 AD27 Address 27
A16 GND Ground
A17 REQ2 Request 2 1
A18 GND Ground
A19 CLK1 33 or 66 MHz Clock
A20 CLK2
A21 GND Ground
A22 CLK3
A23 CLK4
A24 +3,3V +3.3 VDC
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3
B3 +5V +5 VDC
B4 AD8 Address 8
B5 +3,3V +3.3 VDC
B6 AD14 Address 14
B7 PAR Parity
B8 +3,3V +3.3 VDC
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2
B11 V(I/O) +3.3 or +5 VDC
B12 AD21 Address 21
B13 +3,3V +3.3 VDC
B14 V(I/O) +3.3 or +5 VDC
B15 AD28 Address 28
B16 AD31 Address 31
B17 +3,3V +3.3 VDC
B18 GNT3 Grant 3
B19 RST# Reset
B20 NMI# Non Maskable Interrupt
B21 X6 Reserved (6)
B22 +5V +5 VDC :
B23 RSTIN# 2
B24 USB+ Universal Serial Bus (USB)(+)
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground
C3 AD7 Address 7
C4 AD9 Address 9
C5 AD11 Address 11
C6 GND Ground
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground
C11 AD19 Address 19
C12 AD22 Address 22
C13 GND Ground
C14 AD25 Address 25
C15 GND Ground
C16 X1 Reserved (1)
C17 GNT2 Grant 2
C18 REQ4 Request 4 1
C19 SLEEP#/SDAT Sleep/Serial Data (I2C) 3
C20 X4 Reserved (4)
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC
C24 USB- Universal Serial Bus (USB)(-)
D1 AD0 Address 0
D2 AD4 Address 4
D3 C/BE0# Command, Byte Enable 0
D4 +3,3V +3.3 VDC
D5 AD12 Address 12
D6 AD15 Address 15
D7 V(I/O) +3.3 or +5 VDC
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16
D11 AD20 Address 20
D12 +5V +5 VDC
D13 +5V +5 VDC
D14 AD26 Address 26
D15 AD29 Address 29
D16 REQ1 Request 1 1
D17 REQ3 Request 3 1
D18 V(I/O) +3.3 or +5 VDC
D19 X2 Reserved (2)
D20 X5 Reserved (5)
D21 +3,3V +3.3 VDC
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)
E1 AD1 Address 1
E2 AD5 Address 5
E3 GND Ground
E4 M66EN Enable 66Mhz PCI-bus
E5 GND Ground
E6 C/BE1# Command, Byte Enable 1
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC
E9 IRDY# Initatior Ready 1
E10 AD17 Address 17
E11 GND Ground
E12 AD23 Address 23
E13 C/BE3# Command, Byte Enable 3
E14 GND Ground
E15 AD30 Address 30
E16 GNT1 Grant 1
E17 +5V +5 VDC
E18 GNT4 Grant 4
E19 X3 Reserved (3)
E20 GND Ground
E21 INTC# Interrupt C 1
E22 -12V -12 VDC
E23 +12V +12 VDC
E24 VBATT

1 = Pullup resistor of 2,7 kW on the System Slot (CPU).
2 = Pullup resistor of 330 W on the System Slot (CPU).
3 = Pullup resistor of 4,7 kW, if not supported by the System Slot (CPU).

Module Bus Slot (Middle)

PinNameDescriptionNote
A1 +3,3V +3.3 VDC
A2 AD2 Address 2
A3 AD6 Address 6
A4 GND Ground
A5 AD10 Address 10
A6 AD13 Address 13
A7 GND Ground
A8 SDONE Snoop Done 1
A9 GND Ground
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18
A12 GND Ground
A13 +5V +5 VDC
A14 AD24 Address 24
A15 AD27 Address 27
A16 GND Ground
A17 REQ2 Request 2 1
A18 CLKM
A19 CLK1 33 or 66 MHz Clock
A20 CLK2
A21 GND Ground
A22 CLK3
A23 CLK4
A24 +3,3V +3.3 VDC
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3
B3 +5V +5 VDC
B4 AD8 Address 8
B5 +3,3V +3.3 VDC
B6 AD14 Address 14
B7 PAR Parity
B8 +3,3V +3.3 VDC
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2
B11 V(I/O) +3.3 or +5 VDC
B12 AD21 Address 21
B13 +3,3V +3.3 VDC
B14 V(I/O) +3.3 or +5 VDC
B15 AD28 Address 28
B16 AD31 Address 31
B17 +3,3V +3.3 VDC
B18 GNT3 Grant 3
B19 RST# Reset
B20 NMI# Non Maskable Interrupt
B21 X6 Reserved (6)
B22 +5V +5 VDC :
B23 RSTIN#
B24 USB+ Universal Serial Bus (USB)(+)
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground
C3 AD7 Address 7
C4 AD9 Address 9
C5 AD11 Address 11
C6 GND Ground
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground
C11 AD19 Address 19
C12 AD22 Address 22
C13 GND Ground
C14 AD25 Address 25
C15 GND Ground
C16 X1 Reserved (1)
C17 GNT2 Grant 2
C18 REQ4 Request 4 1
C19 SLEEP#/SDAT Sleep/Serial Data (I2C)
C20 X4 Reserved (4)
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC
C24 USB- Universal Serial Bus (USB)(-)
D1 AD0 Address 0
D2 AD4 Address 4
D3 C/BE0# Command, Byte Enable 0
D4 +3,3V +3.3 VDC
D5 AD12 Address 12
D6 AD15 Address 15
D7 V(I/O) +3.3 or +5 VDC
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16
D11 AD20 Address 20
D12 +5V +5 VDC
D13 +5V +5 VDC
D14 AD26 Address 26
D15 AD29 Address 29
D16 REQ1 Request 1 1
D17 REQ3 Request 3 1
D18 V(I/O) +3.3 or +5 VDC
D19 X2 Reserved (2)
D20 X5 Reserved (5)
D21 +3,3V +3.3 VDC
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)
E1 AD1 Address 1
E2 AD5 Address 5
E3 GND Ground
E4 M66EN Enable 66Mhz PCI-bus
E5 GND Ground
E6 C/BE1# Command, Byte Enable 1
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC
E9 IRDY# Initatior Ready 1
E10 AD17 Address 17
E11 GND Ground
E12 AD23 Address 23
E13 C/BE3# Command, Byte Enable 3
E14 GND Ground
E15 AD30 Address 30
E16 GNT1 Grant 1
E17 +5V +5 VDC
E18 GNT4 Grant 4
E19 X3 Reserved (3)
E20 GND Ground
E21 INTC# Interrupt C 1
E22 -12V -12 VDC
E23 +12V +12 VDC
E24 VBATT

1 = Pullup resistor of 2,7 kW on the System Slot (CPU).

Card Slot (Middle)

PinNameDescriptionNote
A1 +3,3V +3.3 VDC
A2 AD2 Address 2
A3 AD6 Address 6
A4 GND Ground
A5 AD10 Address 10
A6 AD13 Address 13
A7 GND Ground
A8 SDONE Snoop Done 1
A9 GND Ground
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18
A12 GND Ground
A13 +5V +5 VDC
A14 AD24 Address 24
A15 AD27 Address 27
A16 GND Ground
A17 IDSEL0 IDSEL0 1
A18 GND Ground
A19 CLK1 33 or 66 MHz Clock
A20 GND Ground
A21 GND Ground
A22 GND Ground
A23 GND Ground
A24 +3,3V +3.3 VDC
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3
B3 +5V +5 VDC
B4 AD8 Address 8
B5 +3,3V +3.3 VDC
B6 AD14 Address 14
B7 PAR Parity
B8 +3,3V +3.3 VDC
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2
B11 V(I/O) +3.3 or +5 VDC
B12 AD21 Address 21
B13 +3,3V +3.3 VDC
B14 V(I/O) +3.3 or +5 VDC
B15 AD28 Address 28
B16 AD31 Address 31
B17 +3,3V +3.3 VDC
B18 GND Ground
B19 RST# Reset
B20 NMI# Non Maskable Interrupt
B21 X6 Reserved (6)
B22 +5V +5 VDC :
B23 RSTIN#
B24 USB+ Universal Serial Bus (USB)(+)
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground
C3 AD7 Address 7
C4 AD9 Address 9
C5 AD11 Address 11
C6 GND Ground
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground
C11 AD19 Address 19
C12 AD22 Address 22
C13 GND Ground
C14 AD25 Address 25
C15 GND Ground
C16 X1 Reserved (1)
C17 IDSEL1 Initialization Device Select 1
C18 GND Ground
C19 SLEEP#/SDAT Sleep/Serial Data (I2C)
C20 X4 Reserved (4)
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC
C24 USB- Universal Serial Bus (USB)(-)
D1 AD0 Address 0
D2 AD4 Address 4
D3 C/BE0# Command, Byte Enable 0
D4 +3,3V +3.3 VDC
D5 AD12 Address 12
D6 AD15 Address 15
D7 V(I/O) +3.3 or +5 VDC
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16
D11 AD20 Address 20
D12 +5V +5 VDC
D13 +5V +5 VDC
D14 AD26 Address 26
D15 AD29 Address 29
D16 REQ1 Request 1 1
D17 IDSEL2 Initialization Device Select 2
D18 V(I/O) +3.3 or +5 VDC
D19 X2 Reserved (2)
D20 X5 Reserved (5)
D21 +3,3V +3.3 VDC
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)
E1 AD1 Address 1
E2 AD5 Address 5
E3 GND Ground
E4 M66EN Enable 66Mhz PCI-bus
E5 GND Ground
E6 C/BE1# Command, Byte Enable 1
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC
E9 IRDY# Initatior Ready 1
E10 AD17 Address 17
E11 GND Ground
E12 AD23 Address 23
E13 C/BE3# Command, Byte Enable 3
E14 GND Ground
E15 AD30 Address 30
E16 GNT1 Grant 1
E17 +5V +5 VDC
E18 GNT4 Grant 4
E19 X3 Reserved (3)
E20 GND Ground
E21 INTC# Interrupt C 1
E22 -12V -12 VDC
E23 +12V +12 VDC
E24 VBATT

1 = Pullup resistor of 2,7 kW on the System Slot (CPU).

64-bit PCI (Top)

PinNameDescriptionNote
A1 GND Ground
A2 X10 Reserved (10)
A3 AD35 Address 35 2
A4 AD38 Address 38 2
A5 AD42 Address 42 2
A6 V(I/O) +3.3 or +5 VDC
A7 V(I/O) +3.3 or +5 VDC
A8 AD52 Address 52 2
A9 AD56 Address 56 2
A10 AD60 Address 60 2
A11 AD63 Address 63 2
A12 GND Ground
B1 X7 Reserved (7)
B2 GND Ground
B3 AD36 Address 36 2
B4 AD39 Address 39 2
B5 AD43 Address 43 2
B6 AD46 Address 46 2
B7 AD49 Address 49 2
B8 AD53 Address 53 2
B9 AD57 Address 57 2
B10 AD61 Address 61 2
B11 GND Ground
B12 C/BE6# Command, Byte Enable 6 2
C1 X8 Reserved (8)
C2 AD32 Address 32 2
C3 GND Ground
C4 AD40 Address 40 2
C5 AD44 Address 44 2
C6 GND Ground
C7 GND Ground
C8 AD54 Address 54 2
C9 AD58 Address 58 2
C10 GND Ground
C11 PAR64 Parity 64 ??? 2
C12 C/BE7# Command, Byte Enable 7 2
D1 X9 Reserved (9)
D2 AD33 Address 33 2
D3 AD37 Address 37 2
D4 GND Ground
D5 AD45 Address 45 2
D6 AD47 Address 47 2
D7 AD50 Address 50 2
D8 AD55 Address 55 2
D9 GND Ground
D10 AD62 Address 62 2
D11 C/BE4# Command, Byte Enable 4 2
D12 X11 Reserved (11)
E1 GND Ground
E2 AD34 Address 34 2
E3 V(I/O) +3.3 or +5 VDC
E4 AD41 Address 41 2
E5 GND Ground
E6 AD48 Address 48 2
E7 AD51 Address 51 2
E8 GND Ground
E9 AD59 Address 59 2
E10 V(I/O) +3.3 or +5 VDC
E11 C/BE5# Command, Byte Enable 5 2
E12 X12 Reserved (12)

2 = Pullup resistor of 2,7 kW (5V bus system) or 8,2 kW (3,3V bus system) on the backplane.

ISA96/AT96 (Bottom)

PinNameDescriptionNote
A1 RSTDRV
A2 IRQ9 Interrupt 9
A3 SD11 Data 11
A4 SD9 Data 9
A5 IOCHRDY 1
A6 IOW# I/O Write
A7 SA15 Address 15
A8 CLK Clock
A9 SA10 Address 10
A10 SA7 Address 7
A11 T/C
A12 SA2 Address 2
B1 SD15 Data 15
B2 SD13 Data 13
B3 SD3 Data 3
B4 SD1 Data 1
B5 SMEMW# System Memory Write
B6 SA18 Address 18
B7 SA14 Address 14
B8 DACK6# DMA Acknowledge 6
B9 SA9 Address 9
B10 IRQ3 Interrupt 3
B11 IOCS16# I/O 16-bit chip select 1
B12 SA1 Address 1
C1 SD7 Data 7
C2 SD5 Data 5
C3 SD10 Data 10
C4 SD8 Data 8
C5 AEN Address Enable
C6 IOR# I/O Read
C7 SA13 Address 13
C8 SA11 Address 11
C9 IRQ5 Interrupt 5
C10 SA6 Address 6
C11 SA4 Address 4
C12 IRQ11 Interrupt 11
D1 SD14 Data 14
D2 SD12 Data 12
D3 SD2 Data 2
D4 SD0 Data 0
D5 SMEMR# System Memory Read
D6 SA17 Address 17
D7 REF#
D8 IRQ7 Interrupt 7
D9 SA8 Address 8
D10 MCS16# 1
D11 BALE
D12 SA0 Address 0
E1 SD6 Data 6
E2 SD4 Data 4
E3 0WS 1
E4 SBHE#
E5 SA19 Address 19
E6 SA16 Address 16
E7 SA12 Address 12
E8 DRQ6 DMA Request 6
E9 IRQ4 Interrupt 4
E10 SA5 Address 5
E11 SA3 Address 3
E12 IRQ10 Interrupt 10

1 = Pullup resistor must be integrated into the System Slot (CPU).

VMEbus (Bottom)

PinNameDescription
A1 D0 Data 0
A2 D2 Data 2
A3 D12 Data 12
A4 D7 Data 7
A5 DS1#
A6 BR3#
A7 AM1
A8 AM3
A9 IACKOUT#
A10 A14 Address 14
A11 A12 Address 12
A12 A10 Address 10
B1 BBSY#
B2 D10 Data 10
B3 D5 Data 5
B4 D15 Data 15
B5 SYSRES#
B6 A23 Address 23
B7 A21 Address 21
B8 A19 Address 19
B9 A16 Address 16
B10 A6 Address 6
B11 A4 Address 4
B12 A2 Address 2
C1 D8 Data 8
C2 D3 Data 3
C3 D13 Data 13
C4 SYSCLK
C5 DS0#
C6 DTACK#
C7 AS#
C8 IACK#
C9 AM4
C10 A13 Address 13
C11 A11 Address 11
C12 A9 Address 9
D1 D1 Data 1
D2 D11 Data 11
D3 D6 Data 6
D4 BG3OUT#
D5 WR# Write
D6 AM0
D7 AM2
D8 A18 Address 18
D9 A15 Address 15
D10 A5 Address 5
D11 A3 Address 3
D12 A1 Address 1
E1 D9 Data 9
E2 D4 Data 4
E3 D14 Data 14
E4 BERR# Bus Error
E5 AM5
E6 A22 Address 22
E7 A20 Address 20
E8 A17 Address 17
E9 A7 Address 7
E10 IRQ5# Interrupt 5
E11 IRQ3# Interrupt 3
E12 A8 Address 8

ECB (Bottom)

PinNameDescription
A1 D5 Data 5
A2 D2 Data 2
A3 A4 Data 4
A4 A7 Address 7
A5 BAI
A6 2F
A7 A10 Address 10
A8 INT#
A9 VCMOS
A10 PWRCLR#
A11 A13 Address 13
A12 RESET# Reset
B1 D0 Data 0
B2 D4 Data 4
B3 A1 Address 1
B4 WAIT#
B5 A17 Address 17
B6 IEO
B7 n/c Not connected
B8 DMARDY
B9 RD# Read
B10 IORQ#
B11 ?
B12 n/c Not connected
C1 D6 Data 6
C2 A0 Address 0
C3 A5 Address 5
C4 A16 Address 16
C5 A18 Address 18
C6 BAO
C7 M1#
C8 WR#
C9 n
C10 A12 Address 12
C11 A9 Address 9
C12 n/c Not connected
D1 D7 Data 7
D2 A2 Address 2
D3 A8 Address 8
D4 BUSRQ#
D5 A19 Address 19
D6 A11 Address 11
D7 NMI# Non Maskable Interrupt
D8 PF
D9 HALT#
D10 RFSH#
D11 MRQ#
D12 n/c Not connected
E1 D3 Data 3
E2 A3 Address 3
E3 A6 Address 6
E4 IEI
E5 D1 Data 1
E6 A14 Address 14
E7 n/c Not connected
E8 n/c Not connected
E9 DESLCT#
E10 A15 Address 15
E11 BUSAK#
E12 n/c Not connected

SMP16 (Bottom)

PinNameDescription
A1 NMI# Non Maskable Interrupt
A2 IRQ0# Interrupt 0
A3 D11 Data 11
A4 D9 Data 9
A5 RDYIN
A6 IOW#
A7 A15 Address 15
A8 CLK
A9 A10 Address 10
A10 A7 Address 7
A11 TC/EOP#
A12 A2 Address 2
B1 D15 Data 15
B2 D13 Data 13
B3 D3 Data 3
B4 D1 Data 1
B5 MEMW#
B6 A18 Address 18
B7 A14 Address 14
B8 DACKx#
B9 A9 Address 9
B10 IRQ3# Interrupt 3
B11 IOCS16#
B12 A1 Address 1
C1 D7 Data 7
C2 D5 Data 5
C3 D10 Data 10
C4 D8 Data 8
C5 BUSEN
C6 IOR#
C7 A13 Address 13
C8 A11 Address 11
C9 IRQ1# Interrupt 1
C10 A6 Address 6
C11 A4 Address 4
C12 IRQ4# Interrupt 4
D1 D14 Data 14
D2 D12 Data 12
D3 D2 Data 2
D4 D0 Data 0
D5 MEMR#
D6 A17 Address 17
D7 INTA#
D8 INT#
D9 A8 Address 8
D10 MECS16#
D11 ALE
D12 A0 Address 0
E1 D6 Data 6
E2 D4 Data 4
E3 MMIO#
E4 BHEN
E5 A19 Address 19
E6 A16 Address 16
E7 A12 Address 12
E8 DRQx#
E9 IRQ2# Interrupt 2
E10 A5 Address 5
E11 A3 Address 3
E12 IRQ5# Interrupt 5

Floppy/EIDE (Bottom)

PinNameDescription
A1 FDSEL1 Floppy Select 1
A2 FDSEL0 Floppy Select 0
A3 FDME1 Floppy ?
A4 DIR Floppy Direction
A5 STEP Floppy Step
A6 WRDATA Floppy Write Data
A7 WE Floppy Write?
A8 TRK0 Floppy Track 0
A9 WP Floppy Write?
A10 RDDATA Floppy ?
A11 HDSEL Floppy HD Select
A12 DSKCHG Floppy DiskChange
B1 DRVDEN1 ?
B2 DRVDEN0 ?
B3 IDECS3P# IDE ?
B4 IDEA2 IDE ?
B5 IDEIRQS IDE ?
B6 IDEPUS IDE ?
B7 IDEDRQP IDE ?
B8 IDED14 IDE Data 14
B9 IDED8 IDE Data 8
B10 IDED6 IDE Data 6
B11 IDED11 IDE Data 11
B12 IDED3 IDE Data 3
C1 FDME0 Floppy Me?
C2 INDX Floppy Index
C3 IDECS3S# IDE ?
C4 IDEA0 IDE ?
C5 IDEDAKS# IDE ?
C6 IDEIOR# IDE ?
C7 IDEDRQS IDE ?
C8 IDED1 IDE Data 1
C9 #IDERST IDE ?
C10 IDED10 IDE Data 10
C11 IDED4 IDE Data 4
C12 IDED2 IDE Data 2
D1 IDELEDS# IDE LED ?
D2 IDELEDP# IDE LED ?
D3 IDECS1S# IDE ?
D4 IDEIRQP IDE ?
D5 IDEPUP IDE Pull Up ?
D6 IDEIOW# IDE ?
D7 IDED15 IDE Data 15
D8 IDED13 IDE Data 13
D9 IDED7 IDE Data 7
D10 GND Ground
D11 GND Ground
D12 GND Ground
E1 GND Ground
E2 GND Ground
E3 IDECS1P# IDE ?
E4 IDEA1 IDE ?
E5 IDEDAKP# IDE ?
E6 IDEIORDY IDE ?
E7 IDED0 IDE Data 0
E8 IDED12 IDE Data 12
E9 IDED9 IDE Data 9
E10 IDED5 IDE Data 5
E11 GND Ground
E12 GND Ground

SCSI (Bottom)

PinNameDescription
A1 TERM
A2 GND Ground
A3 I/O#
A4 REQ#
A5 ATN#
A6 D8 Data 8
A7 D9 Data 9
A8 D10 Data 10
A9 D2 Data 2
A10 D4 Data 4
A11 DP0
A12 GND Ground
B1 TERM
B2 GND Ground
B3 GND Ground
B4 GND Ground
B5 GND Ground
B6 GND Ground
B7 GND Ground
B8 GND Ground
B9 GND Ground
B10 GND Ground
B11 GND Ground
B12 GND Ground
C1 TERM
C2 GND Ground
C3 C/D#
C4 MSG#
C5 ACK#
C6 D12 Data 12
C7 DP1 Data P1
C8 D13 Data 13
C9 D1 Data 1
C10 D5 Data 5
C11 D7 Data 7
C12 GND Ground
D1 TERM
D2 GND Ground
D3 GND Ground
D4 GND Ground
D5 GND Ground
D6 GND Ground
D7 GND Ground
D8 GND Ground
D9 GND Ground
D10 GND Ground
D11 GND Ground
D12 GND Ground
E1 TERM
E2 GND Ground
E3 SEL#
E4 RST#
E5 BSY#
E6 D14 Data 14
E7 D15 Data 15
E8 D11 Data 11
E9 D0 Data 0
E10 D3 Data 3
E11 D6 Data 6
E12 GND Ground
 

CompactPCI (Technical)

This section does not currently contain so much in depth information as I would like.

Since CompactPCI is based on PCI you should first refer to the PCI standard. This only explains the extensions CompactPCI specifies.

For a copy of the full CompactPCI standard, contact:

PCI Industrial Computer Manufacturers Group (PICMG)
c/o Roger Communications
301 Edgewater place
Suite 220
Wakewater
MA01880
Phone: 1-617-224-1100
Fax: 1-617-224-1239

Overview:

A CompactPCI system is composed of up to eight CompactPCI card locations:

  • One System Slot
  • Up to seven Peipherial Slots

The connector has 7 columns with 47 rows. They're divided into groups:

  • Row 1-25: 32-bit PCI
  • Row 26-47: Additional pins for 64-bit PCI (System Slot boards must use it).
  • Row 26-28 and 40-42: Primarily implemented on System Slot boards.

The following signals must be terminated:

  • AD0-31
  • C/BE0#-C/BE3#
  • PAR
  • FRAME#
  • IRDY#
  • TRDY#
  • STOP#
  • LOCK#
  • IDSEL
  • DEVSEL#
  • PERR#
  • SERR#
  • RST#

The following signals must be terminated if used:

  • INTA#
  • INTB#
  • INTC#
  • INTD#
  • SB0#
  • SDOBE
  • AD32-AD63
  • C/BE4#-C/BE7#
  • REQ64#
  • ACK64#
  • PAR64#

The following signals do no require a stub termination:

  • CLK
  • REQ#
  • GNT#
  • TDI#
  • TDO
  • TCK
  • TMS
  • TRST#

The System Slot board must pullup the following signals (even if not used):

  • REQ64#
  • ACK64#

Connector:

1 GND 5V -12V TRST# 12V 5V GND
2 GND TCK 5V TMS DO TDI GND
3 GND INTA# INTB# INTC# 5V INTD# GND
4 GND BRSV GND V(I/O) INTP INTS GND
5 GND BRSV BRSV RST GND GNT# GND
6 GND REQ# GND 3.3V CLK AD(31) GND
7 GND AD(30) AD(29) AD(28) GND AD(27) GND
8 GND AD(26) GND V(I/O) AD(25) AD(24) GND
9 GND C/BE(3)# IDSEL AD(23) GND AD(22) GND
10 GND AD(21) GND 3.3V AD(20) AD(19) GND
11 GND AD(18) AS(17) AD(16) GND C/BE(2)# GND
12 KEY KEY KEY KEY KEY KEY KEY
13 KEY KEY KEY KEY KEY KEY KEY
14 KEY KEY KEY KEY KEY KEY KEY
15 GND 3.3V FRAME# IRDY# GND TRDY# GND
16 GND DEVSEL# GND V(I/O) STOP# LOCK# GND
17 GND 3.3V SDONE SBO# GND PERR# GND
18 GND SERR# GND 3.3V PAR C/BE(1)# GND
19 GND 3.3V AD(15) AD(14) GND AD(13) GND
20 GND AD(12) GND V(I/O) AD(11) AD(10) GND
21 GND 3.3V AD(9) AD(8) M66EN C/BE(0)# GND
22 GND AD(7) GND 3.3V AD(6) AD(5) GND
23 GND 3.3V AD(4) AD(3) 5V AD(2) GND
24 GND AD(1) 5V V(I/O) AD(0) ACK64# GND
25 GND 5V REQ64# BRSV 3.3V 5V GND
26 GND CLK1 GND REQ1# GNT1# REQ2# GND
27 GND CLK2 CLK3 SYSEN# GNT2# REQ3# GND
28 GND CLK4 GND GNT3# REQ4# GNT4# GND
29 GND V(I/O) BRSV C/BE(7 ) GND C/BE(6)# GND
30 GND C/BE(5)# GND V(I/O) C/BE(4)# PAR64 GND
31 GND AD(63) AD(62) AD(61) GND AD(60) GND
32 GND AD(59) GND V(I/O) AD(58) AD(57) GND
33 GND AD(56) AD(55) AD(54) GND AD(53) GND
34 GND AD(52) GND V(I/O) AD(51) AD(50) GND
35 GND AD(49) AD(48) AD(47) GND AD(46) GND
36 GND AD(45) GND V(I/O) AD(44) AD(43) GND
37 GND AD(42) AD(41) AD(40) GND AD(39) GND
38 GND AD(38) GND V(I/O) AD(37) AD(36) GND
39 GND AD(35) AD(34) AD(33) GND AD(32) GND
40 GND BRSV GND FAL# REQ5# GNT5# GND
41 GND BRSV BRSV DEG# GND BRSV GND
42 GND BRSV GND PRST# REQ6# GNT6# GND
43 GND USR USR USR USR USR GND
44 GND USR USR USR USR USR GND
45 GND USR USR USR USR USR GND
46 GND USR USR USR USR USR GND
47 GND USR USR USR USR USR GND
ZABCDEF

Signal Descriptions:

PRST

Push Button Reset.

DEG

Power Supply Status DEG

FAL

Power Supply Status FAL

SYSEN

System Slot Identification

 
 

ISA (Technical)

This file is designed to give a basic overview of the bus found in most IBM clone computers, often referred to as the XT or AT bus. The AT version of the bus is upwardly compatible, which means that cards designed to work on an XT bus will work on an AT bus. This bus was produced for many years without any formal standard. In recent years, a more formal standard called the ISA bus (Industry Standard Architecture) has been created, with an extension called the EISA (Extended ISA) bus also now as a standard. The EISA bus extensions will not be detailed here.

This file is not intended to be a thorough coverage of the standard. It is for informational purposes only, and is intended to give designers and hobbyists sufficient information to design their own XT and AT compatible cards.

Physical Design:

ISA cards can be either 8-bit or 16-bit. 8-bit cards only uses the first 62 pins and 16-bit cards uses all 98 pins. Some 8-bit cards uses some of the 16-bit extension pins to get more interrupts.

8-bit card:

62 PIN EDGE CONNECTOR MALE (At the card)
62 PIN EDGE CONNECTOR FEMALE (At the computer)

16-bit card:

62+36 PIN EDGE CONNECTOR MALE (At the card)
62+36 PIN EDGE CONNECTOR FEMALE (At the computer)

Signal Descriptions:

+5, -5, +12, -12

Power supplies. -5 is often not implimented.

AEN

Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from responding to the I/O command lines during a DMA transfer. When AEN is active, the DMA Controller has control of the address bus as the memory and I/O read/write command lines.

BALE

Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should latch the LA bus on the falling edge of BALE. Some references refer to this signal as Buffered Address Latch Enable, or just Address Latch Enable (ALE). The Buffered-Address Latch Enable is used to latch SA0-19 on the falling edge. This signal is forced high during DMA cycles.

BCLK

Bus Clock, 33% Duty Cycle. Frequency Varies. 4.77 to 8 MHz typical. 8.3 MHz is specified as the maximum, but many systems allow this clock to be set to 12 MHz and higher.

DACKx

DMA Acknowledge. The active-low DMA Acknowledge 0 to 3 and 5 to 7 are the corresponding acknowledge signals for DRQ 0-3, 5-7.

DRQx

DMA Request. These signals are asynchronous channel requests used by I/O channel devices to gain DMA service. DMA request channels 0-3 are for 8-bit data transfer. DAM request channels 5-7 are for 16-bit data transfer. DMA request channel 4 is used internally on the system board. DMA requests should be held high until the corresponding DACK line goes active. DMA requests are serviced in the following priority sequence:
High: DRQ 0, 1, 2, 3, 5, 6, 7 Lowest

IOCS16

I/O size 16. Generated by a 16 bit slave when addressed by a bus master. The active-low I/O Chip Select 16 indicates that the current transfer is a 1 wait state, 16 bit I/O cycle. Open Collector.

I/O CH CK

Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu. The I/O Channel Check is an active-low signal which indicates that a parity error exists in a device on the I/O channel.

I/O CH RDY

Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end the bus cycle. Holding this line low for too long (15 microseconds, typical) can prevent RAM refresh cycles on some systems. This signal is called IOCHRDY (I/O Channel Ready) by some references. CHRDY and NOWS should not be used simultaneously. This may cause problems with some bus controllers. This signal is pulled low by a memory or I/O device to lengthen memory or I/O read/write cycles. It should only be held low for a maimum of 2.5 microseconds.

IOR

The I/O Read is an active-low signal which instrucs the I/O device to drive its data onto the data bus, SD0-SD15.

IOW

The I/O Write is an active-low signal which instructs the I/O device to read data from the data bus, SD0-SD15.

IRQx

Interrupt Request. IRQ2 has the highest priority. IRQ 10-15 are only available on AT machines, and are higher priority than IRQ 3-7. The Interrupt Request signals which indicate I/O service attention. They are prioritized in the following sequence: Highest IRQ 9(2),10,11,12,14,3,4,5,6,7

LAxx

Latchable Address lines. Combine with the lower address lines to form a 24 bit address space (16 MB) These unlatched address signals give the system up to 16 MB of address ability. The are valid when "BALE" is high.

MASTER

16 bit bus master. Generated by the ISA bus master when initiating a bus cycle. This active-low signal is used in conjuction with a DRQ line by a processor on the I/O channel to gain control of the system. The I/O processor first issues a DRQ, and upon recieving the corresponding DACK, the I/O processor may assert MASTER, which will allow it to control the system address, data and control lines. This signal should not be assrted for more than 15 microseconds, or system memory may be corrupted du to the lack of memory refresh activity.

MEMCS16

The active-low Memory Chip Select 16 indicates that the current data transfer is a 1 wait state, 16 bit data memory cycle.

MEMR

The Memory Read is an active-low signal which instructs memory devices to drive data onto the data bus SD0-SD15. This signal is active on all memory read cycles.

MEMW

The Memory Write is an active-low signal which instructs memory devices to store data present on the data bus SD0-SD15. This signal is active on all memory write cycles.

NOWS

No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both signals should not be active simultaneously.

OSC

Oscillator, 14.31818 MHz, 50% Duty Cycle. Frequency varies. This was originally divided by 3 to provide the 4.77 MHz cpu clock of early PCs, and divided by 12 to produce the 1.19 MHz system clock. Some references have placed this signal as low as 1 MHz (possibly referencing the system clock), but most modern systems use 14.318 MHz.
This frequency (14.318 MHz) is four times the television colorburst frequency. Refresh timing on many PC's is based on OSC/18, or approximately one refresh cycle every 15 microseconds. Many modern motherboards allow this rate to be changed, which frees up some bus cycles for use by software, but also can cause memory errors if the system RAM cannot handle the slower refesh rates.

REFRESH

Refresh. Generated when the refresh logic is bus master. This active-low signal is used to indicate a memory refresh cycle is in progress. An ISA device acting as bus master may also use this signal to initiate a refresh cycle.

RESET

This signal goes low when the machine is powered up. Driving it low will force a system reset. This signal goes high to reset the system during powerup, low line-voltage or hardware reset. ??????????????

SA0-SA19

System Address Lines, tri-state. The System Address lines run from bit 0 to bit 19. They are latched on to the falling edge of "BALE".

SBHE

System Bus High Enable, tristate. Indicates a 16 bit data transfer. The System Bus High Enable indicates high byte transfer is occuring on the data bus SD8-SD15. This may also indicate an 8 bit transfer using the upper half of the bus data (if an odd address is present).

SD0-SD16

System Data lines, or Standard Data Lines. They are bidrectional and tri-state. On most systems, the data lines float high when not driven. These 16 lines provide for data transfer between the processor, memory and I/O devices.

SMEMR

System Memory Read Command line. Indicates a memory read in the lower 1 MB area. This System Memory Read is an active-low signal which instructs memory devices to drive data onto the data bus SD0-SD15. This signal is active only when the memory address is within the lowest 1MB of memory address space.

SMEMW

System Memory Write Commmand line. Indicates a memory write in the lower 1 MB area. The System Memory Write is an active-low signal which instructs memory devices to store data preset on the data bus SD0-SD15. This signal is active only when the memory address is within the lowest 1MB of memory address space.

T/C

Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete. Terminal Count provides a pulse when the terminal count for any DMA channel is reached.

8 Bit Memory or I/O Transfer Timing Diagram (4 wait states shown)

                  __     __     __    __     __     __     __
BCLK          ___|  |___|  |___|  |__|  |___|  |___|  |___|  |__
                               W1    W2     W3     W4
                      __
BALE          _______|  |_______________________________________



AEN           __________________________________________________

                        ______________________________________
SA0-SA19      ---------<______________________________________>-


              _____________                                _____
Command Line               |______________________________|
(IORC,IOWC,
SMRDC, or SMWTC)
                                                      _____
SD0-SD7       ---------------------------------------<_____>----
(READ)

                        ___________________________________
SD0-SD7       ---------<___________________________________>----
(WRITE)

Note: W1 through W4 indicate wait cycles.

BALE is placed high, and the address is latched on the SA bus. The slave device may safely sample the address during the falling edge of BALE, and the address on the SA bus remains valid until the end of the transfer cycle. Note that AEN remains low throughout the entire transfer cycle.

The command line is then pulled low (IORC or IOWC for I/O commands, SMRDSC or SMWTC for memory commands, read and write respectively). For write operations, the data remaines on the SD bus for the remainder of the transfer cycle. For read operations, the data must be valid on the falling edge of the last cycle.

NOWS is sampled at the midpoint of each wait cycle. If it is low, the transfer cycle terminates without further wait states. CHRDY is sampled during the first half of the clock cycle. If it is low, further wait cycles will be inserted.

The default for 8 bit transfers is 4 wait states. Some computers allow the number of default wait states to be changed.

16 Bit Memory or I/O Transfer Timing Diagram (1 wait state shown)

                  __     __     __    __     __     __
BCLK          ___|  |___|  |___|  |__|  |___|  |___|  |_


AEN [2]       __________________________________________

                      _____________
LA17-LA23     -------<_____________>-[1]-----------------

                             __
BALE          ______________|  |________________________

             ________________                    _______
SBHE                         |__________________|

                              __________________
SA0-SA19      ---------------<__________________>-------

             _________________      ____________________
M16                           |____|
                               *  * [4]

             _________________               ___________
IO16 [3]                      |_____________|
                                        *

              _________________              ___________
Command Line                   |____________|
(IORC,IOWC,
MRDC, or MWTC)
                                          ____
SD0-SD7       ---------------------------<____>---------
(READ)

                                ______________
SD0-SD7       -----------------<______________>---------
(WRITE)

An asterisk (*) denotes the point where the signal is sampled.

[1] The portion of the address on the LA bus for the NEXT cycle may now be placed on the bus. This is used so that cards may begin decoding the address early. Address pipelining must be active.

[2] AEN remains low throughout the entire transfer cycle, indicating that a normal (non-DMA) transfer is occuring.

[3] Some bus controllers sample this signal during the same clock cycle as M16, instead of during the first wait state, as shown above. In this case, IO16 needs to be pulled low as soon as the address is decoded, which is before the I/O command lines are active.

[4] M16 is sampled a second time, in case the adapter card did not active the signal in time for the first sample (usually because the memory device is not monitoring the LA bus for early address information, or is waiting for the falling edge of BALE).

16 bit transfers follow the same basic timing as 8 bit transfers.A valid address may appear on the LA bus prior to the beginning of the transfer cycle. Unlike the SA bus, the LA bus is not latched, and is not valid for the entire transfer cycle (on most computers). The LA bus should be latched on the falling edge of BALE. Note that on some systems, the LA bus signals will follow the same timing as the SA bus. On either type of system, a valid address is present on the falling edge of BALE.

I/O adapter cards do not need to monitor the LA bus or BALE, since I/O addresses are always within the address space of the SA bus.

SBHE will be pulled low by the system board, and the adapter card must respond with IO16 or M16 at the appropriate time, or else the transfer will be split into two seperate 8 bit transfers. Many systems expect IO16 or M16 before the command lines are valid. This requires that IO16 or M16 be pulled low as soon as the address is decoded (before it is known whether the cycle is I/O or Memory). If the system is starting a memory cycle, it will ignore IO16 (and vice-versa for I/O cycles and M16).

For read operations, the data is sampled on the rising edge of the last clock cycle. For write operations, valid data appears on the bus before the end of the cycle, as shown in the timing diagram. While the timing diagram indicates that the data needs to be sampled on the rising clock, on most systems it remains valid for the entire clock cycle.

The default for 16 bit transfers is 1 wait state. This may be shortened or lengthened in the same manner as 8 bit transfers, via NOWS and CHRDY. Many systems only allow 16 bit memory devices (and not I/O devices) to transfer using 0 wait states (NOWS has no effect on 16 bit I/O cycles).

SMRDC/SMWTC follow the same timing as MRDC/MWTC respectively when the address is within the lower 1 MB. If the address is not within the lower 1 MB boundary, SMRDC/SMWTC will remain high during the entire cycle.

It is also possible for an 8 bit bus cycle to use the upper portion of the bus. In this case, the timing will be similar to a 16 bit cycle, but an odd address will be present on the bus. This means that the bus is transferring 8 bits using the upper data bits (SD8-SD15).

Shortening or Lengthening the bus cycle:

BCLK       W                 W     W                 W
 _    __    __    __    __    __    __    __    __    __    __    __
  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__

        |--Transfer 1-----|----Transfer 2---------|----Transfer 3---|

BALE
         __                __                      __                __
________|  |______________|  |____________________|  |______________|


SBHE
_________                                       _______________________
         |__________________|__________________|


SA0-SA19
           _________________  _____________________  _________________
----------<_________________><_____________________><_________________>


IO16
___________               ___               ___________________________
           |_____________|   |_____________|
                    *                 *

CHRDY
________________________________        _______________________________
                                |______|
                  *                 *     *  [1]

NOWS
______________________________________________________            _____
                                                      |__________|
                                                        * [2]
IORC
______________           _______                 _______           ____
              |_________|       |_______________|       |_________|


SD0-SD15
                     ____                    ____              ____
--------------------<____>------------------<____>------------<____>---
                       *                       *                 *

An asterisk (*) denotes the point where the signal is sampled.
W=Wait Cycle

This timing diagram shows three different transfer cycles. The first is a 16 bit standard I/O read. This is followed by an almost identical 16 bit I/O read, with one wait state inserted. The I/O device pulls CHRDY low to indicate that it is not ready to complete the transfer (see [1]). This inserts a wait cycle, and CHRDY is again sampled. At this second sample, the I/O device has completed its operation and released CHRDY, and the bus cycle now terminates. The third cycle is an 8 bit transfer, which is shortened to 1 wait state (the default is 4) by the use of NOWS.

I/O Port Addresses

Note: Only the first 10 address lines are decoded for I/O operations. This limits the I/O address space to address 3FF (hex) and lower. Some systems allow for 16 bit I/O address space, but may be limited due to some I/O cards only decoding 10 of these 16 bits.

Port (hex) Port Assignments
000-00F DMA Controller
010-01F DMA Controller (PS/2)
020-02F Master Programmable Interrupt Controller (PIC)
030-03F Slave PIC
040-05F Programmable Interval Timer (PIT)
060-06F Keyboard Controller
070-071 Real Time Clock
080-083 DMA Page Register
090-097 Programmable Option Select (PS/2)
0A0-0AF PIC #2
0C0-0CF DMAC #2
0E0-0EF reserved
0F0-0FF Math coprocessor, PCJr Disk Controller
100-10F Programmable Option Select (PS/2)
110-16F AVAILABLE
170-17F Hard Drive 1 (AT)
180-1EF AVAILABLE
1F0-1FF Hard Drive 0 (AT)
200-20F Game Adapter
210-217 Expansion Card Ports
220-26F AVAILABLE
278-27F Parallel Port 3
280-2A1 AVAILABLE
2A2-2A3 clock
2B0-2DF EGA/Video
2E2-2E3 Data Acquisition Adapter (AT)
2E8-2EF Serial Port COM4
2F0-2F7 Reserved
2F8-2FF Serial Port COM2
300-31F Prototype Adapter, Periscope Hardware Debugger
320-32F AVAILABLE
330-33F Reserved for XT/370
340-35F AVAILABLE
360-36F Network
370-377 Floppy Disk Controller
378-37F Parallel Port 2
380-38F SDLC Adapter
390-39F Cluster Adapter
3A0-3AF reserved
3B0-3BF Monochome Adapter
3BC-3BF Parallel Port 1
3C0-3CF EGA/VGA
3D0-3DF Color Graphics Adapter
3E0-3EF Serial Port COM3
3F0-3F7 Floppy Disk Controller
3F8-3FF Serial Port COM1

Soundblaster cards usually use I/O ports 220-22F.
Data acquisition cards frequently use 300-31F.

DMA Read and Write

The ISA bus uses two DMA controllers (DMAC) cascaded together. The slave DMAC connects to the master DMAC via DMA channel 4 (channel 0 on the master DMAC). The slave therefore gains control of the bus through the master DMAC. On the ISA bus, the DMAC is programmed to use fixed priority (channel 0 always has the highest priority), which means that channel 0-4 from the slave have the highest priority (since they connect to the master channel 0), followed by channels 5-7 (which are channel 1-3 on the master).

The DMAC can be programmed for read transfers (data is read from memory and written to the I/O device), write transfers (data is read from the I/O device and written to memory), or verify transfers (neither a read or a write - this was used by DMA CH0 for DRAM refresh on early PCs).

Before a DMA transfer can take place, the DMA Controller (DMAC) must be programmed. This is done by writing the start address and the number of bytes to transfer (called the transfer count) and the direction of the transfer to the DMAC. After the DMAC has been programmed, the device may activate the appropriate DMA request (DRQx) line.

Slave DMA Controller

I/O Port
0000 DMA CH0 Memory Address Register
Contains the lower 16 bits of the memory address, written as two consecutive bytes.
0001 DMA CH0 Transfer Count
Contains the lower 16 bits of the transfer count, written as two consecutive bytes.
0002 DMA CH1 Memory Address Register
0003 DMA CH1 Transfer Count
0004 DMA CH2 Memory Address Register
0005 DMA CH2 Transfer Count
0006 DMA CH3 Memory Address Register
0007 DMA CH3 Transfer Count
0008 DMAC Status/Control Register
Status (I/O read) bits 0-3: Terminal Count, CH 0-3
- bits 4-7: Request CH0-3
Control (write)
- bit 0: Mem to mem enable (1 = enabled)
- bit 1: ch0 address hold enable (1 = enabled)
- bit 2: controller disable (1 = disabled)
- bit 3: timing (0 = normal, 1 = compressed)
- bit 4: priority (0 = fixed, 1 = rotating)
- bit 5: write selection (0 = late, 1 = extended)
- bit 6: DRQx sense asserted (0 = high, 1 = low)
- bit 7: DAKn sense asserted (0 = low, 1 = high)
0009 Software DRQn Request
- bits 0-1: channel select (CH0-3)
- bit 2: request bit (0 = reset, 1 = set)
000A DMA mask register
- bits 0-1: channel select (CH0-3)
- bit 2: mask bit (0 = reset, 1 = set)
000B DMA Mode Register
- bits 0-1: channel select (CH0-3)
- bits 2-3: 00 = verify transfer, 01 = write transfer, 10 = read transfer, 11 = reserved
- bit 4: Auto init (0 = disabled, 1 = enabled)
- bit 5: Address (0 = increment, 1 = decrement)
- bits 6-7: 00 = demand transfer mode, 01 = single transfer mode, 10 = block transfer mode, 11 = cascade mode
000C DMA Clear Byte Pointer
Writing to this causes the DMAC to clear the pointer used to keep track of 16 bit data transfers into and out of the DMAC for hi/low byte sequencing.
000D DMA Master Clear (Hardware Reset)
000E DMA Reset Mask Register - clears the mask register
000F DMA Mask Register
- bits 0-3: mask bits for CH0-3 (0 = not masked, 1 = masked)
0081 DMA CH2 Page Register (address bits A16-A23)
0082 DMA CH3 Page Register
0083 DMA CH1 Page Register
0087 DMA CH0 Page Register
0089 DMA CH6 Page Register
008A DMA CH7 Page Register
008B DMA CH5 Page Register

Master DMA Controller

I/O Port
00C0 DMA CH4 Memory Address Register
Contains the lower 16 bits of the memory address, written as two consecutive bytes.
00C2 DMA CH4 Transfer Count
Contains the lower 16 bits of the transfer count, written as two consecutive bytes.
00C4 DMA CH5 Memory Address Register
00C6 DMA CH5 Transfer Count
00C8 DMA CH6 Memory Address Register
00CA DMA CH6 Transfer Count
00CC DMA CH7 Memory Address Register
00CE DMA CH7 Transfer Count
00D0 DMAC Status/Control Register
Status (I/O read) bits 0-3: Terminal Count, CH 4-7
- bits 4-7: Request CH4-7
Control (write)- bit 0: Mem to mem enable (1 = enabled)
- bit 1: ch0 address hold enable (1 = enabled)
- bit 2: controller disable (1 = disabled)
- bit 3: timing (0 = normal, 1 = compressed)
- bit 4: priority (0 = fixed, 1 = rotating)
- bit 5: write selection (0 = late, 1 = extended)
- bit 6: DRQx sense asserted (0 = high, 1 = low)
- bit 7: DAKn sense asserted (0 = low, 1 = high)
00D2 Software DRQn Request
- bits 0-1: channel select (CH4-7)
- bit 2: request bit (0 = reset, 1 = set)
00D4 DMA mask register
- bits 0-1: channel select (CH4-7)
- bit 2: mask bit (0 = reset, 1 = set)
00D6 DMA Mode Register
- bits 0-1: channel select (CH4-7)
- bits 2-3: 00 = verify transfer, 01 = write transfer, 10 = read transfer, 11 = reserved
- bit 4: Auto init (0 = disabled, 1 = enabled)
- bit 5: Address (0 = increment, 1 = decrement)
- bits 6-7: 00 = demand transfer mode, 01 = single transfer mode, 10 = block transfer mode, 11 = cascade mode
00D8 DMA Clear Byte Pointer
Writing to this causes the DMAC to clear the pointer used to keep track of 16 bit data transfers into and out of the DMAC for hi/low byte sequencing.
00DA DMA Master Clear (Hardware Reset)
00DC DMA Reset Mask Register - clears the mask register
00DE DMA Mask Register
- bits 0-3: mask bits for CH4-7 (0 = not masked, 1 = masked)

Single Transfer Mode

The DMAC is programmed for transfer. The DMA device requests a transfer by driving the appropriate DRQ line high. The DMAC responds by asserting AEN and acknowledges the DMA request through the appropriate DAK line. The I/O and memory command lines are also asserted. When the DMA device sees the DAK signal, it drops the DRQ line.

The DMAC places the memory address on the SA bus (at the same time as the command lines are asserted), and the device either reads from or writes to memory, depending on the type of transfer. The transfer count is incrimented, and the address incrimented/decrimented. DAK is de-asserted. The cpu now once again has control of the bus, and continues execution until the I/O device is once again ready for transfer. The DMA device repeats the procedure, driving DRQ high and waiting for DAK, then transferring data. This continues for a number of cycles equal to the transfer count. When this has been completed, the DMAC signals the cpu that the DMA transfer is complete via the TC (terminal count) signal.

                  __     __     __    __     __     __
BCLK          ___|  |___|  |___|  |__|  |___|  |___|  |___

               _______
DRQx         _|       |___________________________________

                   ______________________________
AEN           ____|                              |________

              _______                             ________
DAKx                 |___________________________|

                      ____________________________
SA0-SA15      -------<____________________________>-------


              ___________                     ____________
Command Line             |___________________|
(IORC, MRDC)
                                     _____________
SD0-SD7       ----------------------<_____________>-------
(READ)

                      ____________________________
SD0-SD7       -------<____________________________>-------
(WRITE)

Block Transfer Mode

The DMAC is programmed for transfer. The device attempting DMA transfer drives the appropriate DRQ line high. The motherboard responds by driving AEN high and DAK low. This indicates that the DMA device is now the bus master. In response to the DAK signal, the DMA device drops DRQ. The DMAC places the address for DMA transfer on the address bus. Both the memory and I/O command lines are asserted (since DMA involves both an I/O and a memory device). AEN prevents I/O devices from responding to the I/O command lines, which would not result in proper operation since the I/O lines are active, but a memory address is on the address bus. The data transfer is now done (memory read or write), and the DMAC incriments/decriments the address and begins another cycle. This continues for a number of cycles equal to the DMAC transfer count. When this has been completed, the terminal count signal (TC) is generated by the DMAC to inform the cpu that the DMA transfer has been completed.

Note: Block transfer must be used carefully. The bus cannot be used for other things (like RAM refresh) while block mode transfers are being done.

Demand Transfer Mode

The DMAC is programmed for transfer. The device attempting DMA transfer drives the appropriate DRQ line high. The motherboard responds by driving AEN high and DAK low. This indicates that the DMA device is now the bus master. Unlike single transfer and block transfer, the DMA device does not drop DRQ in response to DAK. The DMA device transfers data in the same manner as for block transfers. The DMAC will continue to generate DMA cycles as long as the I/O device asserts DRQ. When the I/O device is unable to continue the transfer (if it no longer had data ready to transfer, for example), it drops DRQ and the cpu once again has control of the bus. Control is returned to the DMAC by once again asserting DRQ. This continues until the terminal count has been reached, and the TC signal informs the cpu that the transfer has been completed.

Interrupts on the ISA bus

Name Interrupt Description
NMI 2 Parity Error, Mem Refresh
IRQ0 8 8253 Channel 0 (System Timer)
IRQ1 9 Keyboard
IRQ2 A Cascade from slave PIC
IRQ3 B COM2
IRQ4 C COM1
IRQ5 D LPT2
IRQ6 E Floppy Drive Controller
IRQ7 F LPT1
IRQ8 F Real Time Clock
IRQ9 F Redirection to IRQ2
IRQ10 F Reserved
IRQ11 F Reserved
IRQ12 F Mouse Interface
IRQ13 F Coprocessor
IRQ14 F Hard Drive Controller
IRQ15 F Reserved

IRQ0,1,2,8, and 13 are not available on the ISA bus.

The IBM PC and XT had only a single 8259 interrupt controller. The AT and later machines have a second interrupt controller, and the two are used in a master/slave combination. IRQ2 and IRQ9 are the same pin on most ISA systems. Interrupts on most systems may be either edge triggered or level triggered. The default is usually edge triggered, and active high (low to high transition). The interrupt level must be held high until the first interrupt acknowledge cycle (two interrupt acknowledge bus cycles are generated in response to an interrupt request).

The software aspects of interrupts and interrupt handlers is intentionally omitted from this document, due to the numerous syntactical differences in software tools and the fact that adequate documentation of this topic is usually provided with developement software.

Bus Mastering:

An ISA device may take control of the bus, but this must be done with caution. There are no safety mechanisms involved, and so it is easily possible to crash the entire system by incorrectly taking control of the bus. For example, most systems require bus cycles for DRAM refresh. If the ISA bus master does not relinquish control of the bus or generate its own DRAM refresh cycles every 15 microseconds, the system RAM can become corrupted. The ISA adapter card can generate refresh cycles without relinquishing control of the bus by asserting REFRESH. MRDC can be then monitored to determine when the refresh cycle ends.

To take control of the bus, the device first asserts its DRQ line. The DMAC sends a hold request to the cpu, and when the DMAC receives a hold acknowledge, it asserts the appropriate DAK line corresponding to the DRQ line asserted. The device is now the bus master. AEN is asserted, so if the device wishes to access I/O devices, it must assert MASTER16 to release AEN. Control of the bus is returned to the system board by releasing DRQ.

 
 
0

ISA

  • 23-02-2009, 23:52
  • Просмотров: 3260
 

ISA

ISA=Industry Standard Architecture

62+36 PIN EDGE CONNECTOR MALE (At the card)
62+36 PIN EDGE CONNECTOR FEMALE (At the computer)

62+36 PIN EDGE CONNECTOR MALE at the card.
62+36 PIN EDGE CONNECTOR FEMALE at the computer.

Pin Name Dir Description
A1 /I/O CH CK <-- I/O channel check; active low=parity error
A2 D7 <-> Data bit 7
A3 D6 <-> Data bit 6
A4 D5 <-> Data bit 5
A5 D4 <-> Data bit 4
A6 D3 <-> Data bit 3
A7 D2 <-> Data bit 2
A8 D1 <-> Data bit 1
A9 D0 <-> Data bit 0
A10 I/O CH RDY <-- I/O Channel ready, pulled low to lengthen memory cycles
A11 AEN --> Address enable; active high when DMA controls bus
A12 A19 --> Address bit 19
A13 A18 --> Address bit 18
A14 A17 --> Address bit 17
A15 A16 --> Address bit 16
A16 A15 --> Address bit 15
A17 A14 --> Address bit 14
A18 A13 --> Address bit 13
A19 A12 --> Address bit 12
A20 A11 --> Address bit 11
A21 A10 --> Address bit 10
A22 A9 --> Address bit 9
A23 A8 --> Address bit 8
A24 A7 --> Address bit 7
A25 A6 --> Address bit 6
A26 A5 --> Address bit 5
A27 A4 --> Address bit 4
A28 A3 --> Address bit 3
A29 A2 --> Address bit 2
A30 A1 --> Address bit 1
A31 A0 --> Address bit 0
B1 GND Ground
B2 RESET --> Active high to reset or initialize system logic
B3 +5V +5 VDC
B4 IRQ2 <-- Interrupt Request 2
B5 -5VDC -5 VDC
B6 DRQ2 <-- DMA Request 2
B7 -12VDC -12 VDC
B8 /NOWS <-- No WaitState
B9 +12VDC +12 VDC
B10 GND Ground
B11 /SMEMW --> System Memory Write
B12 /SMEMR --> System Memory Read
B13 /IOW --> I/O Write
B14 /IOR --> I/O Read
B15 /DACK3 --> DMA Acknowledge 3
B16 DRQ3 <-- DMA Request 3
B17 /DACK1 --> DMA Acknowledge 1
B18 DRQ1 <-- DMA Request 1
B19 /REFRESH <-> Refresh
B20 CLOCK --> System Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
B21 IRQ7 <-- Interrupt Request 7
B22 IRQ6 <-- Interrupt Request 6
B23 IRQ5 <-- Interrupt Request 5
B24 IRQ4 <-- Interrupt Request 4
B25 IRQ3 <-- Interrupt Request 3
B26 /DACK2 --> DMA Acknowledge 2
B27 T/C --> Terminal count; pulses high when DMA term. count reached
B28 ALE --> Address Latch Enable
B29 +5V +5 VDC
B30 OSC --> High-speed Clock (70 ns, 1431818 MHz, 50% duty cycle)
B31 GND Ground
C1 SBHE <-> System bus high enable (data availble on SD8-15)
C2 LA23 <-> Address bit 23
C3 LA22 <-> Address bit 22
C4 LA21 <-> Address bit 21
C5 LA20 <-> Address bit 20
C6 LA18 <-> Address bit 19
C7 LA17 <-> Address bit 18
C8 LA16 <-> Address bit 17
C9 /MEMR <-> Memory Read (Active on all memory read cycles)
C10 /MEMW <-> Memory Write (Active on all memory write cycles)
C11 SD08 <-> Data bit 8
C12 SD09 <-> Data bit 9
C13 SD10 <-> Data bit 10
C14 SD11 <-> Data bit 11
C15 SD12 <-> Data bit 12
C16 SD13 <-> Data bit 13
C17 SD14 <-> Data bit 14
C18 SD15 <-> Data bit 15
D1 /MEMCS16 <-- Memory 16-bit chip select (1 wait, 16-bit memory cycle)
D2 /IOCS16 <-- I/O 16-bit chip select (1 wait, 16-bit I/O cycle)
D3 IRQ10 <-- Interrupt Request 10
D4 IRQ11 <-- Interrupt Request 11
D5 IRQ12 <-- Interrupt Request 12
D6 IRQ15 <-- Interrupt Request 15
D7 IRQ14 <-- Interrupt Request 14
D8 /DACK0 --> DMA Acknowledge 0
D9 DRQ0 <-- DMA Request 0
D10 /DACK5 --> DMA Acknowledge 5
D11 DRQ5 <-- DMA Request 5
D12 /DACK6 --> DMA Acknowledge 6
D13 DRQ6 <-- DMA Request 6
D14 /DACK7 --> DMA Acknowledge 7
D15 DRQ7 <-- DMA Request 7
D16 +5 V
D17 /MASTER <-- Used with DRQ to gain control of system
D18 GND Ground
Note: Direction is Motherboard relative ISA-Cards.
Note: B8 was /CARD SLCDTD on the XT. Card selected, activated by cards in XT's slot J8
 
 
0

page_81

  • 7-01-2009, 12:43
  • Просмотров: 2719
Модель: DVDQ50
Глава 5. DVD-проигрыватели Philips

(SD3.1). Этот процессор создан на микропроцес­сорном ядре ST20. Он работает совместно с тре­мя видами памяти: Flash-ROM, SDRAM и EEPROM.
Микросхема памяти Flash-ROM 7401 объемом 16 Мб используется в качестве ПЗУ программ DVD-проигрывателя. БИС 7503 обменивается информацией и управляет работой микросхемы Flash-ROM 7401 через три шины:
- SYSTEM DATA BUS;
- SYSTEM ADDRESS BUS;
- SYSTEM CONTROL BUS .
SDRAM — это синхронное динамическое ОЗУ. Оно обычно составлено из двух микросхем 7404 и 7405, каждая из которых имеет объем 16 Мб, но может использоваться и одна микро­схема объемом 64 Мб. SDRAM выполняет две функции. Первая — это буфер сигнала изобра­жения видеодекодера MPEG, а вторая — опера­тивное хранение кода исполняемых программ и данных, с которыми работают эти программы. Управление работой SDRAM и обмен данными с БИС 7503 осуществляется через SDRAM INTERFACE.
EEPROM (Electrically Erasable and Program­mable Read Only Memory — электрически стирае­мое программируемое постоянное запоминаю­щее устройство, ЭСППЗУ) — это энергонезави­симая память, основное назначение которой — хранение данных при выключенном источнике питания. В проигрывателе DVDQ50 используется микросхема типа 24С32 объемом 32 кб, в кото­рой хранятся все пользовательские и сервисные установки, включая код региона. БИС 7503 свя­зана с микросхемой EEPROM по шине l2C.
Выделенные и преобразованные сигналы DVD, CD или CD-DA от БИС 7311 подаются на главный процессор по шине l2S, где они демуль­типлексируются и поступают на декодер MPEG (MPEG1 и MPEG2). Далее к видеосигналам до­бавляется служебная информация OSD (сигнал экранного меню) и они поступают на кодер PAL/NTSC (внутри микросхемы 7503), где преоб­разуются в следующие аналоговые сигналы со­ответствующих систем:
- сигналы основных цветов RGB или компонен­тные сигналы YUV;
- ПЦТС (CVBS);
- сигналы S-VIDEO (яркостной — Y и сигнал цветности — С).
Эти сигналы поступают плату DTS BOARD или непосредственно на плату A/V board.
На главной плате (моноплате) формируется трехуровневый сигнал, который подается на выв. 8 разъема1609 и обозначается как 0|6|12
(подробнее о особенностях использования этого сигнала см. в описании платы АЛ/ board).
Оцифрованные сигналы звука после демуль-типлексора поступают внутри микросхемы 7503 на аудиодекодер. Этот декодер поддерживает форматы аудиосигналов АС-3, MPEG1, MPEG2, PCM (Pulse Code Modulation — импульсно-кодо-вая модуляция) для БИС STi5508 и STi5580. a для БИС STJ5580 — дополнительно форматы DTS и DVD-audio. Кроме того, микросхема может декодировать потоки данных в сигналы системы 5.1 или в два стереосигнала.
Шесть выходных цифровых мультиплексиро­ванных попарно звуковых сигналов (система 5.1) выводятся непосредственно или через плату DTS BOARD на плату A/V board через следую­щие выводы разъемов главной платы:
— выв. 14 разъема 1603: левый и правый фрон­тальные каналы (PCM_OUT0);
— выв. 6 разъема 1604: центральный канал и ка­нал сабвуфера (PCM_OUT1);
— выв. 4 разъема 1604: левый и правый тыло­вые каналы (PCM_OUT2).
Частоты дискретизации этих сигналов состав­ляют 96, 48, 44,1 или 32 кГц.
Через контакт 21 разъема 1609 на плату DTS BOARD и далее на плату A/V board выводится сигнал (цифровой поток данных) SPDIF. SPDIF (Sony-Philips Digital Interface Format) переводится как формат цифрового интерфейса фирм Sony и Philips.
Еще одна особенность БИС STi5508 и STi5580 заключается в том, что коррекция пре­дыскажений (De-emphasis) сигналов звука осу­ществляется в цифровой форме непосредствен­но в этих БИС. Поэтому на плате A/V board про­игрывателя DVDQ50, который относят к третье­му поколению DVD-проигрывателей, соответствующие цепи коррекции отсутствуют.
Плата DTS-BOARD
Плата DTS (Digital Theatre Sound) Board уста­навливается между главной платой и платой A/V Board только в проигрывателях с главным про­цессором 7503 типа STJ5580. Он обеспечивает демодуляцию сигналов. DTS и DVD-audio и полу­чение полноценных цифровых аудиосигналов в системе 5.1. В процессе ремонта, для проверки работоспособности аппарата и дефектации пла­ты DTS BOARD, ее можно отключить и соответ­ствующие два шлейфа от главной платы вклю­чить непосредственно в разъемы платы A/V bo­ard. Функциональная схема платы DTS-BOARD изображена на рис. 5.6, а принципиальная схема этой платы (в трех частях) показана на трех ри­сунках:
 
 
 
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